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https://github.com/c64scene-ar/llvm-6502.git
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8e7aa4be58
This enables TableGen to generate an additional two operand matcher for our ArithLogicR class of instructions (constituted by 3 register operands). E.g.: and $1, $2 <=> and $1, $1, $2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204826 91177308-0d34-0410-b5e6-96231b3b80d8
26 lines
1.1 KiB
ArmAsm
26 lines
1.1 KiB
ArmAsm
# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=octeon | FileCheck %s
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# CHECK: baddu $9, $6, $7 # encoding: [0x70,0xc7,0x48,0x28]
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# CHECK: baddu $17, $18, $19 # encoding: [0x72,0x53,0x88,0x28]
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# CHECK: dmul $9, $9, $6 # encoding: [0x71,0x26,0x48,0x03]
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# CHECK: dmul $9, $6, $7 # encoding: [0x70,0xc7,0x48,0x03]
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# CHECK: dmul $19, $24, $25 # encoding: [0x73,0x19,0x98,0x03]
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# CHECK: dpop $9, $6 # encoding: [0x70,0xc0,0x48,0x2d]
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# CHECK: dpop $15, $22 # encoding: [0x72,0xc0,0x78,0x2d]
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# CHECK: pop $9, $6 # encoding: [0x70,0xc0,0x48,0x2c]
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# CHECK: pop $8, $19 # encoding: [0x72,0x60,0x40,0x2c]
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# CHECK: seq $25, $23, $24 # encoding: [0x72,0xf8,0xc8,0x2a]
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# CHECK: sne $25, $23, $24 # encoding: [0x72,0xf8,0xc8,0x2b]
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baddu $9, $6, $7
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baddu $17, $18, $19
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dmul $9, $6
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dmul $9, $6, $7
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dmul $19, $24, $25
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dpop $9, $6
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dpop $15, $22
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pop $9, $6
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pop $8, $19
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seq $25, $23, $24
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sne $25, $23, $24
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