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https://github.com/c64scene-ar/llvm-6502.git
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created. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215271 91177308-0d34-0410-b5e6-96231b3b80d8
167 lines
5.2 KiB
C++
167 lines
5.2 KiB
C++
//===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the X86 specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#include "X86TargetMachine.h"
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#include "X86.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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extern "C" void LLVMInitializeX86Target() {
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// Register the target.
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RegisterTargetMachine<X86TargetMachine> X(TheX86_32Target);
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RegisterTargetMachine<X86TargetMachine> Y(TheX86_64Target);
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}
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void X86TargetMachine::anchor() { }
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/// X86TargetMachine ctor - Create an X86 target.
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///
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X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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Subtarget(TT, CPU, FS, *this, Options.StackAlignmentOverride) {
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// default to hard float ABI
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if (Options.FloatABIType == FloatABI::Default)
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this->Options.FloatABIType = FloatABI::Hard;
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// Windows stack unwinder gets confused when execution flow "falls through"
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// after a call to 'noreturn' function.
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// To prevent that, we emit a trap for 'unreachable' IR instructions.
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// (which on X86, happens to be the 'ud2' instruction)
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if (Subtarget.isTargetWin64())
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this->Options.TrapUnreachable = true;
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initAsmInfo();
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}
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//===----------------------------------------------------------------------===//
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// Command line options for x86
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//===----------------------------------------------------------------------===//
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static cl::opt<bool>
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UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
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cl::desc("Minimize AVX to SSE transition penalty"),
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cl::init(true));
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//===----------------------------------------------------------------------===//
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// X86 Analysis Pass Setup
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//===----------------------------------------------------------------------===//
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void X86TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
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// Add first the target-independent BasicTTI pass, then our X86 pass. This
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// allows the X86 pass to delegate to the target independent layer when
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// appropriate.
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PM.add(createBasicTargetTransformInfoPass(this));
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PM.add(createX86TargetTransformInfoPass(this));
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}
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//===----------------------------------------------------------------------===//
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// Pass Pipeline Configuration
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//===----------------------------------------------------------------------===//
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namespace {
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/// X86 Code Generator Pass Configuration Options.
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class X86PassConfig : public TargetPassConfig {
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public:
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X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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X86TargetMachine &getX86TargetMachine() const {
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return getTM<X86TargetMachine>();
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}
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const X86Subtarget &getX86Subtarget() const {
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return *getX86TargetMachine().getSubtargetImpl();
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}
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void addIRPasses() override;
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bool addInstSelector() override;
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bool addILPOpts() override;
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bool addPreRegAlloc() override;
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bool addPostRegAlloc() override;
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bool addPreEmitPass() override;
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};
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} // namespace
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TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
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return new X86PassConfig(this, PM);
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}
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void X86PassConfig::addIRPasses() {
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addPass(createX86AtomicExpandPass(&getX86TargetMachine()));
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TargetPassConfig::addIRPasses();
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}
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bool X86PassConfig::addInstSelector() {
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// Install an instruction selector.
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addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
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// For ELF, cleanup any local-dynamic TLS accesses.
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if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
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addPass(createCleanupLocalDynamicTLSPass());
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addPass(createX86GlobalBaseRegPass());
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return false;
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}
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bool X86PassConfig::addILPOpts() {
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addPass(&EarlyIfConverterID);
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return true;
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}
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bool X86PassConfig::addPreRegAlloc() {
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return false; // -print-machineinstr shouldn't print after this.
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}
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bool X86PassConfig::addPostRegAlloc() {
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addPass(createX86FloatingPointStackifierPass());
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return true; // -print-machineinstr should print after this.
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}
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bool X86PassConfig::addPreEmitPass() {
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bool ShouldPrint = false;
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if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
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addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
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ShouldPrint = true;
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}
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if (UseVZeroUpper) {
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addPass(createX86IssueVZeroUpperPass());
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ShouldPrint = true;
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}
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if (getOptLevel() != CodeGenOpt::None) {
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addPass(createX86PadShortFunctions());
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addPass(createX86FixupLEAs());
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ShouldPrint = true;
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}
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return ShouldPrint;
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}
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bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
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JITCodeEmitter &JCE) {
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PM.add(createX86JITCodeEmitterPass(*this, JCE));
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return false;
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}
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