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1. Teach it to use overlapping unaligned load / store to copy / set the trailing bytes. e.g. On 86, use two pairs of movups / movaps for 17 - 31 byte copies. 2. Use f64 for memcpy / memset on targets where i64 is not legal but f64 is. e.g. x86 and ARM. 3. When memcpy from a constant string, do *not* replace the load with a constant if it's not possible to materialize an integer immediate with a single instruction (required a new target hook: TLI.isIntImmLegal()). 4. Use unaligned load / stores more aggressively if target hooks indicates they are "fast". 5. Update ARM target hooks to use unaligned load / stores. e.g. vld1.8 / vst1.8. Also increase the threshold to something reasonable (8 for memset, 4 pairs for memcpy). This significantly improves Dhrystone, up to 50% on ARM iOS devices. rdar://12760078 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169791 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
CMakeLists.txt | ||
DAGCombiner.cpp | ||
FastISel.cpp | ||
FunctionLoweringInfo.cpp | ||
InstrEmitter.cpp | ||
InstrEmitter.h | ||
LegalizeDAG.cpp | ||
LegalizeFloatTypes.cpp | ||
LegalizeIntegerTypes.cpp | ||
LegalizeTypes.cpp | ||
LegalizeTypes.h | ||
LegalizeTypesGeneric.cpp | ||
LegalizeVectorOps.cpp | ||
LegalizeVectorTypes.cpp | ||
LLVMBuild.txt | ||
Makefile | ||
ResourcePriorityQueue.cpp | ||
ScheduleDAGFast.cpp | ||
ScheduleDAGRRList.cpp | ||
ScheduleDAGSDNodes.cpp | ||
ScheduleDAGSDNodes.h | ||
ScheduleDAGVLIW.cpp | ||
SDNodeDbgValue.h | ||
SDNodeOrdering.h | ||
SelectionDAG.cpp | ||
SelectionDAGBuilder.cpp | ||
SelectionDAGBuilder.h | ||
SelectionDAGDumper.cpp | ||
SelectionDAGISel.cpp | ||
SelectionDAGPrinter.cpp | ||
TargetLowering.cpp | ||
TargetSelectionDAGInfo.cpp |