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6b968eccd7
LDRD<c> <Rt>, <Rt2>, <label>
LDRD<c> <Rt>, <Rt2>, [<Rn>{, #+/-<imm>}]
LDRD<c> <Rt>, <Rt2>, [<Rn>], #+/-<imm>
LDRD<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm>]!
As specified in A8.8.72/A8.8.73 in the ARM ARM, the T1 encoding has a constraint which enforces that Rt != Rt2.
If this constraint is not met the result of executing the instruction will be unpredictable.
Fixes rdar://14479780.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191504 91177308-0d34-0410-b5e6-96231b3b80d8
10 lines
263 B
ArmAsm
10 lines
263 B
ArmAsm
// RUN: not llvm-mc -arch thumb -mattr=+thumb2 \
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// RUN: < %s >/dev/null 2> %t
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// RUN: grep "error: destination operands can't be identical" %t | count 4
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// rdar://14479780
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ldrd r0, r0, [pc, #0]
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ldrd r0, r0, [r1, #4]
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ldrd r0, r0, [r1], #4
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ldrd r0, r0, [r1, #4]!
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