llvm-6502/test/CodeGen/Mips
Akira Hatanaka f09a03776d [mips] Generate big GOT code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168460 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-21 20:40:38 +00:00
..
2008-06-05-Carry.ll
2008-07-03-SRet.ll
2008-07-06-fadd64.ll
2008-07-07-Float2Int.ll
2008-07-07-FPExtend.ll
2008-07-07-IntDoubleConvertions.ll
2008-07-15-InternalConstant.ll
2008-07-15-SmallSection.ll
2008-07-16-SignExtInReg.ll
2008-07-22-Cstpool.ll
2008-07-23-fpcmp.ll
2008-07-29-icmp.ll
2008-07-31-fcopysign.ll
2008-08-01-AsmInline.ll
2008-08-03-fabs64.ll
2008-08-03-ReturnDouble.ll
2008-08-04-Bitconvert.ll
2008-08-06-Alloca.ll
2008-08-07-CC.ll
2008-08-07-FPRound.ll
2008-08-08-bswap.ll
2008-08-08-ctlz.ll
2008-10-13-LegalizerBug.ll
2008-11-10-xint_to_fp.ll
2009-11-16-CstPoolLoad.ll
2010-04-07-DbgValueOtherTargets.ll
2010-07-20-Switch.ll
2010-11-09-CountLeading.ll
2010-11-09-Mul.ll
2011-05-26-BranchKillsVreg.ll
addc.ll
addressing-mode.ll Initial implementation of MipsTargetLowering::isLegalAddressingMode. 2012-11-17 00:25:41 +00:00
alloca16.ll Implement ADJCALLSTACKUP and ADJCALLSTACKDOWN 2012-10-31 05:21:10 +00:00
alloca.ll
analyzebranch.ll
and1.ll
asm-large-immediate.ll
atomic.ll [mips] Fix bug in test case. Disable machine LICM to prevent instruction from 2012-11-02 21:46:42 +00:00
atomicops.ll Expand all atomic ops for mips16. 2012-10-29 16:16:54 +00:00
biggot.ll [mips] Generate big GOT code. 2012-11-21 20:40:38 +00:00
blockaddr.ll
br-jmp.ll
brconeq.ll Add conditional branch instructions and their patterns. 2012-10-17 22:29:54 +00:00
brconeqk.ll Add conditional branch instructions and their patterns. 2012-10-17 22:29:54 +00:00
brconeqz.ll Add conditional branch instructions and their patterns. 2012-10-17 22:29:54 +00:00
brconge.ll Add conditional branch instructions and their patterns. 2012-10-17 22:29:54 +00:00
brcongt.ll Add conditional branch instructions and their patterns. 2012-10-17 22:29:54 +00:00
brconle.ll Add conditional branch instructions and their patterns. 2012-10-17 22:29:54 +00:00
brconlt.ll Add conditional branch instructions and their patterns. 2012-10-17 22:29:54 +00:00
brconne.ll Add conditional branch instructions and their patterns. 2012-10-17 22:29:54 +00:00
brconnek.ll Add conditional branch instructions and their patterns. 2012-10-17 22:29:54 +00:00
brconnez.ll Add conditional branch instructions and their patterns. 2012-10-17 22:29:54 +00:00
brdelayslot.ll [mips] Fix delay slot filler so that instructions with register operand $1 are 2012-11-16 02:39:34 +00:00
brind.ll Implement brind operator for mips16. 2012-10-28 23:08:07 +00:00
bswap.ll
buildpairextractelementf64.ll
check-noat.ll [mips] Delete MipsFunctionInfo::EmitNOAT. Unconditionally print directive 2012-11-02 20:56:25 +00:00
cmov.ll
constantfp0.ll
cprestore.ll
div_rem.ll Div, Rem int/unsigned int 2012-10-12 02:01:09 +00:00
div.ll Div, Rem int/unsigned int 2012-10-12 02:01:09 +00:00
divrem.ll
divu_remu.ll Div, Rem int/unsigned int 2012-10-12 02:01:09 +00:00
divu.ll Div, Rem int/unsigned int 2012-10-12 02:01:09 +00:00
double2int.ll
dsp-r1.ll MIPS DSP: add operands to make sure instruction strings are being matched. 2012-09-28 21:23:16 +00:00
dsp-r2.ll MIPS DSP: add operands to make sure instruction strings are being matched. 2012-09-28 21:23:16 +00:00
eh-dwarf-cfa.ll [mips] Custom-lower ISD::FRAME_TO_ARGS_OFFSET node. 2012-11-07 19:10:58 +00:00
eh.ll
extins.ll
fabs.ll
fastcc.ll
fcopysign-f32-f64.ll
fcopysign.ll
fmadd1.ll
fneg.ll
fp-indexed-ls.ll
fp-spill-reload.ll
fpbr.ll
frame-address.ll
frem.ll
global-address.ll
global-pointer-reg.ll
gprestore.ll
helloworld.ll Change mips16 delay slot jumps to non delay slot forms by default. 2012-10-30 00:54:49 +00:00
i32k.ll implement large (>16 bit) constant loading. 2012-10-26 03:09:34 +00:00
i64arg.ll
imm.ll
indirectcall.ll
init-array.ll Fix UseInitArray option for MIPS target. 2012-09-05 06:17:17 +00:00
inlineasm64.ll
inlineasm_constraint.ll
inlineasm-cnstrnt-bad-I-1.ll
inlineasm-cnstrnt-bad-J.ll
inlineasm-cnstrnt-bad-K.ll
inlineasm-cnstrnt-bad-L.ll
inlineasm-cnstrnt-bad-N.ll
inlineasm-cnstrnt-bad-O.ll
inlineasm-cnstrnt-bad-P.ll
inlineasm-cnstrnt-reg64.ll
inlineasm-cnstrnt-reg.ll
inlineasm-operand-code.ll
inlineasmmemop.ll
internalfunc.ll
largeimm1.ll [mips] Use register number instead of name to print register $AT. 2012-11-02 21:26:03 +00:00
largeimmprinting.ll [mips] Stop reserving register AT and use register scavenger when a scratch 2012-11-03 00:05:43 +00:00
lb1.ll
lbu1.ll
lh1.ll
lhu1.ll
lit.local.cfg
llcarry.ll Implement carry for subtract/add for mips16 2012-10-26 04:46:26 +00:00
load-store-left-right.ll
longbranch.ll [mips] Use register number instead of name to print register $AT. 2012-11-02 21:26:03 +00:00
machineverifier.ll
madd-msub.ll
memcpy.ll
mips64-fp-indexed-ls.ll
mips64-sret.ll [mips] Make sure sret argument is returned in register V0. 2012-10-24 02:10:54 +00:00
mips64countleading.ll
mips64directive.ll
mips64ext.ll
mips64extins.ll
mips64fpimm0.ll
mips64fpldst.ll
mips64imm.ll
mips64instrs.ll
mips64intldst.ll
mips64lea.ll
mips64load-store-left-right.ll
mips64muldiv.ll
mips64shift.ll
mipslopat.ll
misha.ll Implement patterns for extloadi8 and extloadi16 2012-10-29 19:39:04 +00:00
mul.ll Patch for integer multiply, signed/unsigned, long/long long. 2012-10-05 18:27:54 +00:00
mulll.ll Patch for integer multiply, signed/unsigned, long/long long. 2012-10-05 18:27:54 +00:00
mulull.ll Patch for integer multiply, signed/unsigned, long/long long. 2012-10-05 18:27:54 +00:00
neg1.ll
not1.ll
null.ll Change mips16 delay slot jumps to non delay slot forms by default. 2012-10-30 00:54:49 +00:00
o32_cc_byval.ll [mips] Make sure FuncArg doesn't advance when OrigArgIndex is the same as in the 2012-10-27 00:44:39 +00:00
o32_cc_vararg.ll
o32_cc.ll
or1.ll
private.ll
ra-allocatable.ll
rdhwr-directives.ll
rem.ll Div, Rem int/unsigned int 2012-10-12 02:01:09 +00:00
remat-immed-load.ll [mips] Set flag isAsCheapAsAMove flag on instruction LUi. 2012-11-03 00:26:02 +00:00
remu.ll Div, Rem int/unsigned int 2012-10-12 02:01:09 +00:00
return_address.ll
return-vector-float4.ll
return-vector.ll Implement MipsTargetLowering::CanLowerReturn. 2012-10-10 01:27:09 +00:00
rotate.ll
sb1.ll
select.ll
selectcc.ll
selpat.ll implement mips16 patterns for select nodes 2012-10-25 21:33:30 +00:00
seteq.ll implement setXX patterns 2012-10-23 01:35:48 +00:00
seteqz.ll implement setXX patterns 2012-10-23 01:35:48 +00:00
setge.ll implement setXX patterns 2012-10-23 01:35:48 +00:00
setgek.ll fix test setgek.ll so that it will not give false "make check" 2012-10-26 01:29:42 +00:00
setle.ll implement setXX patterns 2012-10-23 01:35:48 +00:00
setlt.ll implement setXX patterns 2012-10-23 01:35:48 +00:00
setltk.ll implement setXX patterns 2012-10-23 01:35:48 +00:00
setne.ll implement setXX patterns 2012-10-23 01:35:48 +00:00
setuge.ll implement setXX patterns 2012-10-23 01:35:48 +00:00
setugt.ll implement setXX patterns 2012-10-23 01:35:48 +00:00
setule.ll implement setXX patterns 2012-10-23 01:35:48 +00:00
setult.ll implement setXX patterns 2012-10-23 01:35:48 +00:00
setultk.ll implement setXX patterns 2012-10-23 01:35:48 +00:00
sh1.ll
shift-parts.ll
sitofp-selectcc-opt.ll
sll1.ll
sll2.ll
small-section-reserve-gp.ll In MipsDAGToDAGISel::SelectAddr, fold add node into address operand, if its 2012-08-24 20:21:49 +00:00
sra1.ll
sra2.ll
srl1.ll
srl2.ll
stacksize.ll
stchar.ll This patch is for the implementation of mips16 complex pattern addr16. 2012-10-28 06:02:37 +00:00
stldst.ll checking test case for r164811. was an omission to not check this in. this was already approved 2012-10-01 21:35:06 +00:00
sub1.ll
sub2.ll
swzero.ll
tailcall.ll Test case for r167039. Check that tail-call optimization is disabled for 2012-10-31 17:25:23 +00:00
tls16_2.ll Implement MipsHi for mips16 2012-10-27 00:57:14 +00:00
tls16.ll implement mips16 tls global addr 2012-10-26 22:57:32 +00:00
tls-alias.ll
tls-models.ll
tls.ll
uitofp.ll Fix bug 13532. 2012-08-28 02:12:42 +00:00
ul1.ll Handled unaligned load/stores properly in Mips16 2012-09-15 01:02:03 +00:00
unalignedload.ll
vector-load-store.ll MIPS DSP: add vector load/store patterns. 2012-09-27 01:50:59 +00:00
weak.ll
xor1.ll
zeroreg.ll