mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-22 07:32:48 +00:00
bcd8e7ad4d
We were generating intrinsics for NEON fixed-point conversions that didn't
exist (e.g. float -> i16). There are two cases to consider:
+ iN is smaller than float. In this case we can do the conversion but need an
extend or truncate as well.
+ iN is larger than float. In this case using the NEON conversion would be
incorrect so we don't perform any combining.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185158 91177308-0d34-0410-b5e6-96231b3b80d8
200 lines
6.0 KiB
LLVM
200 lines
6.0 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon,+fp16 | FileCheck %s
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define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind {
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;CHECK: vcvt_f32tos32:
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;CHECK: vcvt.s32.f32
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%tmp1 = load <2 x float>* %A
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%tmp2 = fptosi <2 x float> %tmp1 to <2 x i32>
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ret <2 x i32> %tmp2
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}
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define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind {
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;CHECK: vcvt_f32tou32:
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;CHECK: vcvt.u32.f32
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%tmp1 = load <2 x float>* %A
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%tmp2 = fptoui <2 x float> %tmp1 to <2 x i32>
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ret <2 x i32> %tmp2
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}
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define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind {
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;CHECK: vcvt_s32tof32:
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;CHECK: vcvt.f32.s32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = sitofp <2 x i32> %tmp1 to <2 x float>
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ret <2 x float> %tmp2
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}
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define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind {
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;CHECK: vcvt_u32tof32:
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;CHECK: vcvt.f32.u32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = uitofp <2 x i32> %tmp1 to <2 x float>
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ret <2 x float> %tmp2
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}
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define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind {
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;CHECK: vcvtQ_f32tos32:
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;CHECK: vcvt.s32.f32
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%tmp1 = load <4 x float>* %A
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%tmp2 = fptosi <4 x float> %tmp1 to <4 x i32>
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ret <4 x i32> %tmp2
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}
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define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind {
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;CHECK: vcvtQ_f32tou32:
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;CHECK: vcvt.u32.f32
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%tmp1 = load <4 x float>* %A
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%tmp2 = fptoui <4 x float> %tmp1 to <4 x i32>
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ret <4 x i32> %tmp2
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}
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define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind {
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;CHECK: vcvtQ_s32tof32:
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;CHECK: vcvt.f32.s32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = sitofp <4 x i32> %tmp1 to <4 x float>
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ret <4 x float> %tmp2
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}
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define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind {
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;CHECK: vcvtQ_u32tof32:
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;CHECK: vcvt.f32.u32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = uitofp <4 x i32> %tmp1 to <4 x float>
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ret <4 x float> %tmp2
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}
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define <2 x i32> @vcvt_n_f32tos32(<2 x float>* %A) nounwind {
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;CHECK: vcvt_n_f32tos32:
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;CHECK: vcvt.s32.f32
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%tmp1 = load <2 x float>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float> %tmp1, i32 1)
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ret <2 x i32> %tmp2
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}
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define <2 x i32> @vcvt_n_f32tou32(<2 x float>* %A) nounwind {
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;CHECK: vcvt_n_f32tou32:
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;CHECK: vcvt.u32.f32
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%tmp1 = load <2 x float>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float> %tmp1, i32 1)
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ret <2 x i32> %tmp2
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}
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define <2 x float> @vcvt_n_s32tof32(<2 x i32>* %A) nounwind {
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;CHECK: vcvt_n_s32tof32:
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;CHECK: vcvt.f32.s32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
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ret <2 x float> %tmp2
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}
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define <2 x float> @vcvt_n_u32tof32(<2 x i32>* %A) nounwind {
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;CHECK: vcvt_n_u32tof32:
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;CHECK: vcvt.f32.u32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
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ret <2 x float> %tmp2
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}
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declare <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float>, i32) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float>, i32) nounwind readnone
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declare <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
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declare <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
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define <4 x i32> @vcvtQ_n_f32tos32(<4 x float>* %A) nounwind {
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;CHECK: vcvtQ_n_f32tos32:
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;CHECK: vcvt.s32.f32
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%tmp1 = load <4 x float>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %tmp1, i32 1)
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ret <4 x i32> %tmp2
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}
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define <4 x i32> @vcvtQ_n_f32tou32(<4 x float>* %A) nounwind {
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;CHECK: vcvtQ_n_f32tou32:
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;CHECK: vcvt.u32.f32
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%tmp1 = load <4 x float>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> %tmp1, i32 1)
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ret <4 x i32> %tmp2
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}
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define <4 x float> @vcvtQ_n_s32tof32(<4 x i32>* %A) nounwind {
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;CHECK: vcvtQ_n_s32tof32:
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;CHECK: vcvt.f32.s32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
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ret <4 x float> %tmp2
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}
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define <4 x float> @vcvtQ_n_u32tof32(<4 x i32>* %A) nounwind {
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;CHECK: vcvtQ_n_u32tof32:
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;CHECK: vcvt.f32.u32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
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ret <4 x float> %tmp2
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}
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declare <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float>, i32) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float>, i32) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
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define <4 x float> @vcvt_f16tof32(<4 x i16>* %A) nounwind {
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;CHECK: vcvt_f16tof32:
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;CHECK: vcvt.f32.f16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = call <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16> %tmp1)
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ret <4 x float> %tmp2
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}
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define <4 x i16> @vcvt_f32tof16(<4 x float>* %A) nounwind {
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;CHECK: vcvt_f32tof16:
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;CHECK: vcvt.f16.f32
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%tmp1 = load <4 x float>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float> %tmp1)
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ret <4 x i16> %tmp2
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}
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declare <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float>) nounwind readnone
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define <4 x i16> @fix_float_to_i16(<4 x float> %in) {
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; CHECK: fix_float_to_i16:
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; CHECK: vcvt.u32.f32 [[TMP:q[0-9]+]], {{q[0-9]+}}, #1
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; CHECK: vmovn.i32 {{d[0-9]+}}, [[TMP]]
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%scale = fmul <4 x float> %in, <float 2.0, float 2.0, float 2.0, float 2.0>
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%conv = fptoui <4 x float> %scale to <4 x i16>
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ret <4 x i16> %conv
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}
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define <2 x i64> @fix_float_to_i64(<2 x float> %in) {
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; CHECK: fix_float_to_i64:
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; CHECK: bl
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; CHECK: bl
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%scale = fmul <2 x float> %in, <float 2.0, float 2.0>
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%conv = fptoui <2 x float> %scale to <2 x i64>
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ret <2 x i64> %conv
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}
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define <4 x i16> @fix_double_to_i16(<4 x double> %in) {
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; CHECK: fix_double_to_i16:
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; CHECK: vcvt.s32.f64
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; CHECK: vcvt.s32.f64
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%scale = fmul <4 x double> %in, <double 2.0, double 2.0, double 2.0, double 2.0>
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%conv = fptoui <4 x double> %scale to <4 x i16>
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ret <4 x i16> %conv
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}
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define <2 x i64> @fix_double_to_i64(<2 x double> %in) {
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; CHECK: fix_double_to_i64:
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; CHECK: bl
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; CHECK: bl
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%scale = fmul <2 x double> %in, <double 2.0, double 2.0>
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%conv = fptoui <2 x double> %scale to <2 x i64>
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ret <2 x i64> %conv
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}
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