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https://github.com/c64scene-ar/llvm-6502.git
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14c09b81ea
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23813 91177308-0d34-0410-b5e6-96231b3b80d8
113 lines
4.1 KiB
C++
113 lines
4.1 KiB
C++
//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "PPCInstrInfo.h"
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#include "PPCGenInstrInfo.inc"
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#include "PPC.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include <iostream>
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using namespace llvm;
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PPCInstrInfo::PPCInstrInfo()
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: TargetInstrInfo(PPCInsts, sizeof(PPCInsts)/sizeof(PPCInsts[0])) {}
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bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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unsigned& destReg) const {
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MachineOpCode oc = MI.getOpcode();
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if (oc == PPC::OR4 || oc == PPC::OR8 ||
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oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2
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assert(MI.getNumOperands() == 3 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() &&
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MI.getOperand(2).isRegister() &&
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"invalid PPC OR instruction!");
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if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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} else if (oc == PPC::ADDI) { // addi r1, r2, 0
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assert(MI.getNumOperands() == 3 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(2).isImmediate() &&
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"invalid PPC ADDI instruction!");
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if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) {
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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} else if (oc == PPC::ORI) { // ori r1, r2, 0
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assert(MI.getNumOperands() == 3 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() &&
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MI.getOperand(2).isImmediate() &&
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"invalid PPC ORI instruction!");
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if (MI.getOperand(2).getImmedValue()==0) {
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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} else if (oc == PPC::FMRS || oc == PPC::FMRD ||
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oc == PPC::FMRSD) { // fmr r1, r2
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assert(MI.getNumOperands() == 2 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() &&
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"invalid PPC FMR instruction");
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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} else if (oc == PPC::MCRF) { // mcrf cr1, cr2
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assert(MI.getNumOperands() == 2 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() &&
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"invalid PPC MCRF instruction");
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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return false;
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}
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// commuteInstruction - We can commute rlwimi instructions, but only if the
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// rotate amt is zero. We also have to munge the immediates a bit.
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MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
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// Normal instructions can be commuted the obvious way.
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if (MI->getOpcode() != PPC::RLWIMI)
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return TargetInstrInfo::commuteInstruction(MI);
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// Cannot commute if it has a non-zero rotate count.
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if (MI->getOperand(3).getImmedValue() != 0)
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return 0;
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// If we have a zero rotate count, we have:
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// M = mask(MB,ME)
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// Op0 = (Op1 & ~M) | (Op2 & M)
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// Change this to:
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// M = mask((ME+1)&31, (MB-1)&31)
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// Op0 = (Op2 & ~M) | (Op1 & M)
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// Swap op1/op2
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unsigned Reg1 = MI->getOperand(1).getReg();
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unsigned Reg2 = MI->getOperand(2).getReg();
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MI->SetMachineOperandReg(2, Reg1);
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MI->SetMachineOperandReg(1, Reg2);
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// Swap the mask around.
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unsigned MB = MI->getOperand(4).getImmedValue();
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unsigned ME = MI->getOperand(5).getImmedValue();
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MI->getOperand(4).setImmedValue((ME+1) & 31);
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MI->getOperand(5).setImmedValue((MB-1) & 31);
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return MI;
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}
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