Jack Carter 37ef65b9c1 This patch that sets the EmitAlias flag in td files ... and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174358 91177308-0d34-0410-b5e6-96231b3b80d8		2013-02-05 08:32:10 +00:00
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2008-06-05-Carry.ll
2008-07-03-SRet.ll
2008-07-06-fadd64.ll
2008-07-07-Float2Int.ll
2008-07-07-FPExtend.ll
2008-07-07-IntDoubleConvertions.ll
2008-07-15-InternalConstant.ll
2008-07-15-SmallSection.ll
2008-07-16-SignExtInReg.ll
2008-07-22-Cstpool.ll
2008-07-23-fpcmp.ll
2008-07-29-icmp.ll
2008-07-31-fcopysign.ll
2008-08-01-AsmInline.ll
2008-08-03-fabs64.ll
2008-08-03-ReturnDouble.ll
2008-08-04-Bitconvert.ll
2008-08-06-Alloca.ll
2008-08-07-CC.ll
2008-08-07-FPRound.ll
2008-08-08-bswap.ll
2008-08-08-ctlz.ll
2008-10-13-LegalizerBug.ll
2008-11-10-xint_to_fp.ll
2009-11-16-CstPoolLoad.ll
2010-04-07-DbgValueOtherTargets.ll
2010-07-20-Switch.ll
2010-11-09-CountLeading.ll
2010-11-09-Mul.ll
2011-05-26-BranchKillsVreg.ll
2012-12-12-ExpandMemcpy.ll
addc.ll
addressing-mode.ll
alloca16.ll
alloca.ll
analyzebranch.ll
and1.ll
asm-large-immediate.ll
atomic.ll
atomicops.ll
biggot.ll
blockaddr.ll
br-jmp.ll
brconeq.ll
brconeqk.ll
brconeqz.ll
brconge.ll
brcongt.ll
brconle.ll
brconlt.ll
brconne.ll
brconnek.ll
brconnez.ll
brdelayslot.ll
brind.ll
bswap.ll
buildpairextractelementf64.ll
check-noat.ll
cmov.ll
constantfp0.ll
cprestore.ll
div_rem.ll
div.ll
divrem.ll
divu_remu.ll
divu.ll
double2int.ll
dsp-r1.ll
dsp-r2.ll
eh-dwarf-cfa.ll
eh-return32.ll
eh-return64.ll
eh.ll
ex2.ll
extins.ll
fabs.ll
fastcc.ll
fcopysign-f32-f64.ll
fcopysign.ll
fmadd1.ll
fneg.ll
fp-indexed-ls.ll
fp-spill-reload.ll
fpbr.ll
frame-address.ll	This patch that sets the EmitAlias flag in td files	2013-02-05 08:32:10 +00:00
frem.ll
global-address.ll
global-pointer-reg.ll
gpreg-lazy-binding.ll
gprestore.ll
helloworld.ll
hf16_1.ll
i32k.ll
i64arg.ll
imm.ll
indirectcall.ll
init-array.ll
inlineasm64.ll
inlineasm_constraint.ll
inlineasm-cnstrnt-bad-I-1.ll
inlineasm-cnstrnt-bad-J.ll
inlineasm-cnstrnt-bad-K.ll
inlineasm-cnstrnt-bad-L.ll
inlineasm-cnstrnt-bad-N.ll
inlineasm-cnstrnt-bad-O.ll
inlineasm-cnstrnt-bad-P.ll
inlineasm-cnstrnt-reg64.ll
inlineasm-cnstrnt-reg.ll
inlineasm-operand-code.ll
inlineasmmemop.ll
internalfunc.ll
largeimm1.ll
largeimmprinting.ll
lb1.ll
lbu1.ll
lh1.ll
lhu1.ll
lit.local.cfg
llcarry.ll
load-store-left-right.ll
longbranch.ll
machineverifier.ll
madd-msub.ll
memcpy.ll
mips16ex.ll
mips16fpe.ll
mips64-fp-indexed-ls.ll
mips64-sret.ll
mips64countleading.ll
mips64directive.ll
mips64ext.ll
mips64extins.ll
mips64fpimm0.ll
mips64fpldst.ll
mips64imm.ll
mips64instrs.ll
mips64intldst.ll
mips64lea.ll
mips64load-store-left-right.ll
mips64muldiv.ll
mips64shift.ll
mipslopat.ll
misha.ll
mul.ll
mulll.ll
mulull.ll
neg1.ll
not1.ll
null.ll
o32_cc_byval.ll
o32_cc_vararg.ll
o32_cc.ll
or1.ll
private.ll
ra-allocatable.ll
rdhwr-directives.ll
rem.ll
remat-immed-load.ll
remu.ll
return_address.ll
return-vector-float4.ll
return-vector.ll
rotate.ll
sb1.ll
select.ll
selectcc.ll
selpat.ll
seteq.ll
seteqz.ll
setge.ll
setgek.ll
setle.ll
setlt.ll
setltk.ll
setne.ll
setuge.ll
setugt.ll
setule.ll
setult.ll
setultk.ll
sh1.ll
shift-parts.ll
sitofp-selectcc-opt.ll
sll1.ll
sll2.ll
small-section-reserve-gp.ll
sra1.ll
sra2.ll
srl1.ll
srl2.ll
stacksize.ll
stchar.ll
stldst.ll
sub1.ll
sub2.ll
swzero.ll
tailcall.ll
tls16_2.ll
tls16.ll
tls-alias.ll
tls-models.ll
tls.ll
uitofp.ll
ul1.ll
unalignedload.ll
vector-load-store.ll
vector-setcc.ll
weak.ll
xor1.ll
zeroreg.ll