Jim Grosbach e43862b6a6 ARM assembly parsing for register range syntax for VLD/VST register lists. ... For example, vld1.f64 {d2-d5}, [r2,:128]! Should be equivalent to: vld1.f64 {d2,d3,d4,d5}, [r2,:128]! It's not documented syntax in the ARM ARM, but it is consistent with what's accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to support. rdar://10451128 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144727 91177308-0d34-0410-b5e6-96231b3b80d8		2011-11-15 23:19:15 +00:00
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Analysis	Don't forget to check FlagNW when determining whether an AddRecExpr will wrap	2011-11-09 07:11:37 +00:00
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MC	ARM assembly parsing for register range syntax for VLD/VST register lists.	2011-11-15 23:19:15 +00:00
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