mirror of
https://github.com/c64scene-ar/llvm-6502.git
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1. Legalize now always promotes truncstore of i1 to i8. 2. Remove patterns and gunk related to truncstore i1 from targets. 3. Rename the StoreXAction stuff to TruncStoreAction in TLI. 4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions. 5. Mark a wide variety of invalid truncstores as such in various targets, e.g. X86 currently doesn't support truncstore of any of its integer types. 6. Add legalize support for truncstores with invalid value input types. 7. Add a dag combine transform to turn store(truncate) into truncstore when safe. The later allows us to compile CodeGen/X86/storetrunc-fp.ll to: _foo: fldt 20(%esp) fldt 4(%esp) faddp %st(1) movl 36(%esp), %eax fstps (%eax) ret instead of: _foo: subl $4, %esp fldt 24(%esp) fldt 8(%esp) faddp %st(1) fstps (%esp) movl 40(%esp), %eax movss (%esp), %xmm0 movss %xmm0, (%eax) addl $4, %esp ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46140 91177308-0d34-0410-b5e6-96231b3b80d8
697 lines
26 KiB
C++
697 lines
26 KiB
C++
//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that Mips uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-lower"
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#include "MipsISelLowering.h"
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#include "MipsMachineFunction.h"
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#include "MipsTargetMachine.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/CallingConv.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/Support/Debug.h"
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#include <queue>
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#include <set>
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using namespace llvm;
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const char *MipsTargetLowering::
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getTargetNodeName(unsigned Opcode) const
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{
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switch (Opcode)
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{
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case MipsISD::JmpLink : return "MipsISD::JmpLink";
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case MipsISD::Hi : return "MipsISD::Hi";
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case MipsISD::Lo : return "MipsISD::Lo";
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case MipsISD::Ret : return "MipsISD::Ret";
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default : return NULL;
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}
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}
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MipsTargetLowering::
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MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
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{
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// Mips does not have i1 type, so use i32 for
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// setcc operations results (slt, sgt, ...).
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setSetCCResultType(MVT::i32);
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setSetCCResultContents(ZeroOrOneSetCCResult);
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// JumpTable targets must use GOT when using PIC_
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setUsesGlobalOffsetTable(true);
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// Set up the register classes
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addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
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// Custom
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setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
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setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
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setOperationAction(ISD::RET, MVT::Other, Custom);
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setOperationAction(ISD::JumpTable, MVT::i32, Custom);
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// Load extented operations for i1 types must be promoted
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setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
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setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
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setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
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// Mips does not have these NodeTypes below.
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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setOperationAction(ISD::BR_CC, MVT::Other, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
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setOperationAction(ISD::SELECT, MVT::i32, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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// Mips not supported intrinsics.
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setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
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setOperationAction(ISD::MEMSET, MVT::Other, Expand);
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setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
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setOperationAction(ISD::CTPOP, MVT::i32, Expand);
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setOperationAction(ISD::CTTZ , MVT::i32, Expand);
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setOperationAction(ISD::CTLZ , MVT::i32, Expand);
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setOperationAction(ISD::ROTL , MVT::i32, Expand);
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setOperationAction(ISD::ROTR , MVT::i32, Expand);
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setOperationAction(ISD::BSWAP, MVT::i32, Expand);
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setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
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// We don't have line number support yet.
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setOperationAction(ISD::LOCATION, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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setOperationAction(ISD::LABEL, MVT::Other, Expand);
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// Use the default for now
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setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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setStackPointerRegisterToSaveRestore(Mips::SP);
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computeRegisterProperties();
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}
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SDOperand MipsTargetLowering::
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LowerOperation(SDOperand Op, SelectionDAG &DAG)
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{
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switch (Op.getOpcode())
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{
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case ISD::CALL: return LowerCALL(Op, DAG);
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case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
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case ISD::RET: return LowerRET(Op, DAG);
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case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
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case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
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case ISD::JumpTable: return LowerJumpTable(Op, DAG);
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}
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return SDOperand();
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}
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//===----------------------------------------------------------------------===//
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// Lower helper functions
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//===----------------------------------------------------------------------===//
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// AddLiveIn - This helper function adds the specified physical register to the
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// MachineFunction as a live in value. It also creates a corresponding
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// virtual register for it.
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static unsigned
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AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
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{
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assert(RC->contains(PReg) && "Not the correct regclass!");
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unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
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MF.getRegInfo().addLiveIn(PReg, VReg);
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return VReg;
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}
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//===----------------------------------------------------------------------===//
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// Misc Lower Operation implementation
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//===----------------------------------------------------------------------===//
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SDOperand MipsTargetLowering::
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LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
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{
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SDOperand ResNode;
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GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
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SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
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bool isPIC = (getTargetMachine().getRelocationModel() == Reloc::PIC_);
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SDOperand HiPart;
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if (!isPIC) {
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const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::i32);
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SDOperand Ops[] = { GA };
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HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
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} else // Emit Load from Global Pointer
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HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0);
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// On functions and global targets not internal linked only
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// a load from got/GP is necessary for PIC to work.
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if ((isPIC) && ((!GV->hasInternalLinkage()) || (isa<Function>(GV))))
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return HiPart;
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SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
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ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
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return ResNode;
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}
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SDOperand MipsTargetLowering::
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LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG)
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{
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assert(0 && "TLS not implemented for MIPS.");
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}
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SDOperand MipsTargetLowering::
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LowerJumpTable(SDOperand Op, SelectionDAG &DAG)
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{
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SDOperand ResNode;
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SDOperand HiPart;
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MVT::ValueType PtrVT = Op.getValueType();
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JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
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SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
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if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
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const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::i32);
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SDOperand Ops[] = { JTI };
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HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
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} else // Emit Load from Global Pointer
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HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), JTI, NULL, 0);
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SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI);
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ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
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return ResNode;
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}
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//===----------------------------------------------------------------------===//
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// Calling Convention Implementation
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//
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// The lower operations present on calling convention works on this order:
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// LowerCALL (virt regs --> phys regs, virt regs --> stack)
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// LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
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// LowerRET (virt regs --> phys regs)
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// LowerCALL (phys regs --> virt regs)
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//
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//===----------------------------------------------------------------------===//
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#include "MipsGenCallingConv.inc"
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//===----------------------------------------------------------------------===//
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// CALL Calling Convention Implementation
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//===----------------------------------------------------------------------===//
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/// Mips custom CALL implementation
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SDOperand MipsTargetLowering::
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LowerCALL(SDOperand Op, SelectionDAG &DAG)
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{
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unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
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// By now, only CallingConv::C implemented
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switch (CallingConv)
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{
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default:
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assert(0 && "Unsupported calling convention");
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case CallingConv::Fast:
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case CallingConv::C:
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return LowerCCCCallTo(Op, DAG, CallingConv);
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}
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}
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/// LowerCCCCallTo - functions arguments are copied from virtual
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/// regs to (physical regs)/(stack frame), CALLSEQ_START and
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/// CALLSEQ_END are emitted.
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/// TODO: isVarArg, isTailCall, sret.
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SDOperand MipsTargetLowering::
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LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
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{
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MachineFunction &MF = DAG.getMachineFunction();
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unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
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SDOperand Chain = Op.getOperand(0);
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SDOperand Callee = Op.getOperand(4);
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bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
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MachineFrameInfo *MFI = MF.getFrameInfo();
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// Analyze operands of the call, assigning locations to each operand.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
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// To meet ABI, Mips must always allocate 16 bytes on
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// the stack (even if less than 4 are used as arguments)
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int VTsize = MVT::getSizeInBits(MVT::i32)/8;
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MFI->CreateFixedObject(VTsize, (VTsize*3));
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CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
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// Get a count of how many bytes are to be pushed on the stack.
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unsigned NumBytes = CCInfo.getNextStackOffset();
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Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
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getPointerTy()));
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SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
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SmallVector<SDOperand, 8> MemOpChains;
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SDOperand StackPtr;
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int LastStackLoc=0;
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// Walk the register/memloc assignments, inserting copies/loads.
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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// Arguments start after the 5 first operands of ISD::CALL
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SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
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// Promote the value if needed.
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switch (VA.getLocInfo()) {
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default: assert(0 && "Unknown loc info!");
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case CCValAssign::Full: break;
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case CCValAssign::SExt:
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Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
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break;
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case CCValAssign::ZExt:
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Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
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break;
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case CCValAssign::AExt:
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Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
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break;
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}
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// Arguments that can be passed on register must be kept at
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// RegsToPass vector
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if (VA.isRegLoc()) {
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RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
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} else {
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assert(VA.isMemLoc());
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if (StackPtr.Val == 0)
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StackPtr = DAG.getRegister(StackReg, getPointerTy());
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// Create the frame index object for this incoming parameter
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// This guarantees that when allocating Local Area the firsts
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// 16 bytes which are alwayes reserved won't be overwritten.
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LastStackLoc = (16 + VA.getLocMemOffset());
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int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
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LastStackLoc);
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SDOperand PtrOff = DAG.getFrameIndex(FI,getPointerTy());
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// emit ISD::STORE whichs stores the
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// parameter value to a stack Location
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MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
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}
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}
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// Transform all store nodes into one single node because
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// all store nodes are independent of each other.
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if (!MemOpChains.empty())
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Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
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&MemOpChains[0], MemOpChains.size());
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// Build a sequence of copy-to-reg nodes chained together with token
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// chain and flag operands which copy the outgoing args into registers.
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// The InFlag in necessary since all emited instructions must be
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// stuck together.
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SDOperand InFlag;
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for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
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Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
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RegsToPass[i].second, InFlag);
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InFlag = Chain.getValue(1);
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}
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// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
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// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
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// node so that legalize doesn't hack it.
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
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Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
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else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
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Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
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// MipsJmpLink = #chain, #target_address, #opt_in_flags...
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// = Chain, Callee, Reg#1, Reg#2, ...
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//
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// Returns a chain & a flag for retval copy to use.
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SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
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SmallVector<SDOperand, 8> Ops;
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Ops.push_back(Chain);
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Ops.push_back(Callee);
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// Add argument registers to the end of the list so that they are
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// known live into the call.
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for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
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Ops.push_back(DAG.getRegister(RegsToPass[i].first,
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RegsToPass[i].second.getValueType()));
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if (InFlag.Val)
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Ops.push_back(InFlag);
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Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
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InFlag = Chain.getValue(1);
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// Create a stack location to hold GP when PIC is used. This stack
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// location is used on function prologue to save GP and also after all
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// emited CALL's to restore GP.
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if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
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// Function can have an arbitrary number of calls, so
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// hold the LastStackLoc with the biggest offset.
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int FI;
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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if (LastStackLoc >= MipsFI->getGPStackOffset()) {
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LastStackLoc = (!LastStackLoc) ? (16) : (LastStackLoc+4);
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// Create the frame index only once. SPOffset here can be anything
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// (this will be fixed on processFunctionBeforeFrameFinalized)
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if (MipsFI->getGPStackOffset() == -1) {
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FI = MFI->CreateFixedObject(4, 0);
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MipsFI->setGPFI(FI);
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}
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MipsFI->setGPStackOffset(LastStackLoc);
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}
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// Reload GP value.
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FI = MipsFI->getGPFI();
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SDOperand FIN = DAG.getFrameIndex(FI,getPointerTy());
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SDOperand GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0);
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Chain = GPLoad.getValue(1);
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Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32),
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GPLoad, SDOperand(0,0));
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}
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// Create the CALLSEQ_END node.
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Chain = DAG.getCALLSEQ_END(Chain,
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DAG.getConstant(NumBytes, getPointerTy()),
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DAG.getConstant(0, getPointerTy()),
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InFlag);
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InFlag = Chain.getValue(1);
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// Handle result values, copying them out of physregs into vregs that we
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// return.
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return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
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}
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/// LowerCallResult - Lower the result values of an ISD::CALL into the
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/// appropriate copies out of appropriate physical registers. This assumes that
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/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
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/// being lowered. Returns a SDNode with the same number of values as the
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/// ISD::CALL.
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SDNode *MipsTargetLowering::
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LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
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unsigned CallingConv, SelectionDAG &DAG) {
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bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
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// Assign locations to each value returned by this call.
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
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CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
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SmallVector<SDOperand, 8> ResultVals;
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// Copy all of the result registers out of their specified physreg.
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
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RVLocs[i].getValVT(), InFlag).getValue(1);
|
|
InFlag = Chain.getValue(2);
|
|
ResultVals.push_back(Chain.getValue(0));
|
|
}
|
|
|
|
ResultVals.push_back(Chain);
|
|
|
|
// Merge everything together with a MERGE_VALUES node.
|
|
return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
|
|
&ResultVals[0], ResultVals.size()).Val;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// FORMAL_ARGUMENTS Calling Convention Implementation
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// Mips custom FORMAL_ARGUMENTS implementation
|
|
SDOperand MipsTargetLowering::
|
|
LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG)
|
|
{
|
|
unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
|
|
switch(CC)
|
|
{
|
|
default:
|
|
assert(0 && "Unsupported calling convention");
|
|
case CallingConv::C:
|
|
return LowerCCCArguments(Op, DAG);
|
|
}
|
|
}
|
|
|
|
/// LowerCCCArguments - transform physical registers into
|
|
/// virtual registers and generate load operations for
|
|
/// arguments places on the stack.
|
|
/// TODO: isVarArg, sret
|
|
SDOperand MipsTargetLowering::
|
|
LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
|
|
{
|
|
SDOperand Root = Op.getOperand(0);
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
|
|
|
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
|
|
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
|
|
|
|
unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
|
|
|
|
// GP holds the GOT address on PIC calls.
|
|
if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
|
|
AddLiveIn(MF, Mips::GP, Mips::CPURegsRegisterClass);
|
|
|
|
// Assign locations to all of the incoming arguments.
|
|
SmallVector<CCValAssign, 16> ArgLocs;
|
|
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
|
|
|
|
CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
|
|
SmallVector<SDOperand, 8> ArgValues;
|
|
SDOperand StackPtr;
|
|
|
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
|
|
|
CCValAssign &VA = ArgLocs[i];
|
|
|
|
// Arguments stored on registers
|
|
if (VA.isRegLoc()) {
|
|
MVT::ValueType RegVT = VA.getLocVT();
|
|
TargetRegisterClass *RC;
|
|
|
|
if (RegVT == MVT::i32)
|
|
RC = Mips::CPURegsRegisterClass;
|
|
else
|
|
assert(0 && "support only Mips::CPURegsRegisterClass");
|
|
|
|
// Transform the arguments stored on
|
|
// physical registers into virtual ones
|
|
unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
|
|
SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
|
|
|
|
// If this is an 8 or 16-bit value, it is really passed promoted
|
|
// to 32 bits. Insert an assert[sz]ext to capture this, then
|
|
// truncate to the right size.
|
|
if (VA.getLocInfo() == CCValAssign::SExt)
|
|
ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
|
|
DAG.getValueType(VA.getValVT()));
|
|
else if (VA.getLocInfo() == CCValAssign::ZExt)
|
|
ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
|
|
DAG.getValueType(VA.getValVT()));
|
|
|
|
if (VA.getLocInfo() != CCValAssign::Full)
|
|
ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
|
|
|
|
ArgValues.push_back(ArgValue);
|
|
|
|
// To meet ABI, when VARARGS are passed on registers, the registers
|
|
// must have their values written to the caller stack frame.
|
|
if (isVarArg) {
|
|
|
|
if (StackPtr.Val == 0)
|
|
StackPtr = DAG.getRegister(StackReg, getPointerTy());
|
|
|
|
// The stack pointer offset is relative to the caller stack frame.
|
|
// Since the real stack size is unknown here, a negative SPOffset
|
|
// is used so there's a way to adjust these offsets when the stack
|
|
// size get known (on EliminateFrameIndex). A dummy SPOffset is
|
|
// used instead of a direct negative address (which is recorded to
|
|
// be used on emitPrologue) to avoid mis-calc of the first stack
|
|
// offset on PEI::calculateFrameObjectOffsets.
|
|
// Arguments are always 32-bit.
|
|
int FI = MFI->CreateFixedObject(4, 0);
|
|
MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
|
|
SDOperand PtrOff = DAG.getFrameIndex(FI, getPointerTy());
|
|
|
|
// emit ISD::STORE whichs stores the
|
|
// parameter value to a stack Location
|
|
ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0));
|
|
}
|
|
|
|
} else {
|
|
// sanity check
|
|
assert(VA.isMemLoc());
|
|
|
|
// The stack pointer offset is relative to the caller stack frame.
|
|
// Since the real stack size is unknown here, a negative SPOffset
|
|
// is used so there's a way to adjust these offsets when the stack
|
|
// size get known (on EliminateFrameIndex). A dummy SPOffset is
|
|
// used instead of a direct negative address (which is recorded to
|
|
// be used on emitPrologue) to avoid mis-calc of the first stack
|
|
// offset on PEI::calculateFrameObjectOffsets.
|
|
// Arguments are always 32-bit.
|
|
int FI = MFI->CreateFixedObject(4, 0);
|
|
MipsFI->recordLoadArgsFI(FI, -(4+(16+VA.getLocMemOffset())));
|
|
|
|
// Create load nodes to retrieve arguments from the stack
|
|
SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
|
|
ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
|
|
}
|
|
}
|
|
ArgValues.push_back(Root);
|
|
|
|
// Return the new list of results.
|
|
return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
|
|
&ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Return Value Calling Convention Implementation
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
SDOperand MipsTargetLowering::
|
|
LowerRET(SDOperand Op, SelectionDAG &DAG)
|
|
{
|
|
// CCValAssign - represent the assignment of
|
|
// the return value to a location
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
|
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
|
|
bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
|
|
|
|
// CCState - Info about the registers and stack slot.
|
|
CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
|
|
|
|
// Analize return values of ISD::RET
|
|
CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips);
|
|
|
|
// If this is the first return lowered for this function, add
|
|
// the regs to the liveout set for the function.
|
|
if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i)
|
|
if (RVLocs[i].isRegLoc())
|
|
DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
|
|
}
|
|
|
|
// The chain is always operand #0
|
|
SDOperand Chain = Op.getOperand(0);
|
|
SDOperand Flag;
|
|
|
|
// Copy the result values into the output registers.
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i) {
|
|
CCValAssign &VA = RVLocs[i];
|
|
assert(VA.isRegLoc() && "Can only return in registers!");
|
|
|
|
// ISD::RET => ret chain, (regnum1,val1), ...
|
|
// So i*2+1 index only the regnums
|
|
Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
|
|
|
|
// guarantee that all emitted copies are
|
|
// stuck together, avoiding something bad
|
|
Flag = Chain.getValue(1);
|
|
}
|
|
|
|
// Return on Mips is always a "jr $ra"
|
|
if (Flag.Val)
|
|
return DAG.getNode(MipsISD::Ret, MVT::Other,
|
|
Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
|
|
else // Return Void
|
|
return DAG.getNode(MipsISD::Ret, MVT::Other,
|
|
Chain, DAG.getRegister(Mips::RA, MVT::i32));
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Mips Inline Assembly Support
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// getConstraintType - Given a constraint letter, return the type of
|
|
/// constraint it is for this target.
|
|
MipsTargetLowering::ConstraintType MipsTargetLowering::
|
|
getConstraintType(const std::string &Constraint) const
|
|
{
|
|
if (Constraint.size() == 1) {
|
|
// Mips specific constrainy
|
|
// GCC config/mips/constraints.md
|
|
//
|
|
// 'd' : An address register. Equivalent to r
|
|
// unless generating MIPS16 code.
|
|
// 'y' : Equivalent to r; retained for
|
|
// backwards compatibility.
|
|
//
|
|
switch (Constraint[0]) {
|
|
default : break;
|
|
case 'd':
|
|
case 'y':
|
|
return C_RegisterClass;
|
|
break;
|
|
}
|
|
}
|
|
return TargetLowering::getConstraintType(Constraint);
|
|
}
|
|
|
|
std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
|
|
getRegForInlineAsmConstraint(const std::string &Constraint,
|
|
MVT::ValueType VT) const
|
|
{
|
|
if (Constraint.size() == 1) {
|
|
switch (Constraint[0]) {
|
|
case 'r':
|
|
return std::make_pair(0U, Mips::CPURegsRegisterClass);
|
|
break;
|
|
}
|
|
}
|
|
return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
|
|
}
|
|
|
|
std::vector<unsigned> MipsTargetLowering::
|
|
getRegClassForInlineAsmConstraint(const std::string &Constraint,
|
|
MVT::ValueType VT) const
|
|
{
|
|
if (Constraint.size() != 1)
|
|
return std::vector<unsigned>();
|
|
|
|
switch (Constraint[0]) {
|
|
default : break;
|
|
case 'r':
|
|
// GCC Mips Constraint Letters
|
|
case 'd':
|
|
case 'y':
|
|
return make_vector<unsigned>(Mips::V0, Mips::V1, Mips::A0,
|
|
Mips::A1, Mips::A2, Mips::A3,
|
|
Mips::T0, Mips::T1, Mips::T2,
|
|
Mips::T3, Mips::T4, Mips::T5,
|
|
Mips::T6, Mips::T7, Mips::S0,
|
|
Mips::S1, Mips::S2, Mips::S3,
|
|
Mips::S4, Mips::S5, Mips::S6,
|
|
Mips::S7, Mips::T8, Mips::T9, 0);
|
|
break;
|
|
}
|
|
return std::vector<unsigned>();
|
|
}
|