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d0fde30ce8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9903 91177308-0d34-0410-b5e6-96231b3b80d8
48 lines
1.5 KiB
C++
48 lines
1.5 KiB
C++
//===- MRegisterInfo.cpp - Target Register Information Implementation -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the MRegisterInfo interface.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/MRegisterInfo.h"
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namespace llvm {
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MRegisterInfo::MRegisterInfo(const MRegisterDesc *D, unsigned NR,
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regclass_iterator RCB, regclass_iterator RCE,
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int CFSO, int CFDO)
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: Desc(D), NumRegs(NR), RegClassBegin(RCB), RegClassEnd(RCE) {
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assert(NumRegs < FirstVirtualRegister &&
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"Target has too many physical registers!");
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PhysRegClasses = new const TargetRegisterClass*[NumRegs];
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for (unsigned i = 0; i != NumRegs; ++i)
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PhysRegClasses[i] = 0;
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// Fill in the PhysRegClasses map
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for (MRegisterInfo::regclass_iterator I = regclass_begin(),
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E = regclass_end(); I != E; ++I)
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for (unsigned i = 0, e = (*I)->getNumRegs(); i != e; ++i) {
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unsigned Reg = (*I)->getRegister(i);
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assert(PhysRegClasses[Reg] == 0 && "Register in more than one class?");
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PhysRegClasses[Reg] = *I;
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}
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CallFrameSetupOpcode = CFSO;
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CallFrameDestroyOpcode = CFDO;
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}
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MRegisterInfo::~MRegisterInfo() {
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delete[] PhysRegClasses;
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}
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} // End llvm namespace
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