Jim Grosbach 383a810b12 ARM: Constrain regclass for TSTri instruction. ...

Get the register class right for the TST instruction. This keeps the
machine verifier happy, enabling us to turn it on for another test.

rdar://12594152

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189274 91177308-0d34-0410-b5e6-96231b3b80d8

2013-08-26 20:22:05 +00:00

..

Analysis

Remove trailing spaces.

2013-08-24 14:16:00 +00:00

AsmParser

Add function attribute 'optnone'.

2013-08-23 11:53:55 +00:00

Bitcode

Add function attribute 'optnone'.

2013-08-23 11:53:55 +00:00

CodeGen

SelectionDAG: Remove unnecessary uses of TargetLowering::getPointerTy()

2013-08-26 15:06:10 +00:00

DebugInfo

Make DWARFCompileUnit non-copyable

2013-08-23 06:56:01 +00:00

ExecutionEngine

Reorder headers according to lint.

2013-08-21 21:14:19 +00:00

IR

Fix a bug where we would corrupt the offset when evaluating

2013-08-25 10:46:39 +00:00

IRReader

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Linker

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MC

MC CFG: Remap enough for data too, analoguous to r188873.

2013-08-21 19:40:28 +00:00

Object

Move #includes from .h to .cpp file.

2013-08-21 01:20:11 +00:00

Option

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Support

Added const qualifier to StringRef::edit_distance member function

2013-08-24 01:50:41 +00:00

TableGen

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Target

ARM: Constrain regclass for TSTri instruction.

2013-08-26 20:22:05 +00:00

Transforms

test commit. Remove blank line

2013-08-26 18:57:55 +00:00

CMakeLists.txt

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LLVMBuild.txt

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Makefile

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