mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-25 00:29:20 +00:00
Summary: Backends can use setInsertFencesForAtomic to signal to the middle-end that montonic is the only memory ordering they can accept for stores/loads/rmws/cmpxchg. The code lowering those accesses with a stronger ordering to fences + monotonic accesses is currently living in SelectionDAGBuilder.cpp. In this patch I propose moving this logic out of it for several reasons: - There is lots of redundancy to avoid: extremely similar logic already exists in AtomicExpand. - The current code in SelectionDAGBuilder does not use any target-hooks, it does the same transformation for every backend that requires it - As a result it is plain *unsound*, as it was apparently designed for ARM. It happens to mostly work for the other targets because they are extremely conservative, but Power for example had to switch to AtomicExpand to be able to use lwsync safely (see r218331). - Because it produces IR-level fences, it cannot be made sound ! This is noted in the C++11 standard (section 29.3, page 1140): ``` Fences cannot, in general, be used to restore sequential consistency for atomic operations with weaker ordering semantics. ``` It can also be seen by the following example (called IRIW in the litterature): ``` atomic<int> x = y = 0; int r1, r2, r3, r4; Thread 0: x.store(1); Thread 1: y.store(1); Thread 2: r1 = x.load(); r2 = y.load(); Thread 3: r3 = y.load(); r4 = x.load(); ``` r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all seq_cst. But if they are lowered to monotonic accesses, no amount of fences can prevent it.. This patch does three things (I could cut it into parts, but then some of them would not be tested/testable, please tell me if you would prefer that): - it provides a default implementation for emitLeadingFence/emitTrailingFence in terms of IR-level fences, that mimic the original logic of SelectionDAGBuilder. As we saw above, this is unsound, but the best that can be done without knowing the targets well (and there is a comment warning about this risk). - it then switches Mips/Sparc/XCore to use AtomicExpand, relying on this default implementation (that exactly replicates the logic of SelectionDAGBuilder, so no functional change) - it finally erase this logic from SelectionDAGBuilder as it is dead-code. Ideally, each target would define its own override for emitLeading/TrailingFence using target-specific fences, but I do not know the Sparc/Mips/XCore memory model well enough to do this, and they appear to be dealing fine with the ARM-inspired default expansion for now (probably because they are overly conservative, as Power was). If anyone wants to compile fences more agressively on these platforms, the long comment should make it clear why he should first override emitLeading/TrailingFence. Test Plan: make check-all, no functional change Reviewers: jfb, t.p.northover Subscribers: aemerson, llvm-commits Differential Revision: http://reviews.llvm.org/D5474 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219957 91177308-0d34-0410-b5e6-96231b3b80d8
233 lines
8.5 KiB
C++
233 lines
8.5 KiB
C++
//===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// Implements the info about Mips target spec.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "MipsTargetMachine.h"
|
|
#include "Mips.h"
|
|
#include "Mips16FrameLowering.h"
|
|
#include "Mips16HardFloat.h"
|
|
#include "Mips16ISelDAGToDAG.h"
|
|
#include "Mips16ISelLowering.h"
|
|
#include "Mips16InstrInfo.h"
|
|
#include "MipsFrameLowering.h"
|
|
#include "MipsInstrInfo.h"
|
|
#include "MipsModuleISelDAGToDAG.h"
|
|
#include "MipsOs16.h"
|
|
#include "MipsSEFrameLowering.h"
|
|
#include "MipsSEISelDAGToDAG.h"
|
|
#include "MipsSEISelLowering.h"
|
|
#include "MipsSEInstrInfo.h"
|
|
#include "llvm/Analysis/TargetTransformInfo.h"
|
|
#include "llvm/CodeGen/Passes.h"
|
|
#include "llvm/PassManager.h"
|
|
#include "llvm/Support/Debug.h"
|
|
#include "llvm/Support/TargetRegistry.h"
|
|
#include "llvm/Support/raw_ostream.h"
|
|
#include "llvm/Transforms/Scalar.h"
|
|
using namespace llvm;
|
|
|
|
#define DEBUG_TYPE "mips"
|
|
|
|
extern "C" void LLVMInitializeMipsTarget() {
|
|
// Register the target.
|
|
RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
|
|
RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
|
|
RegisterTargetMachine<MipsebTargetMachine> A(TheMips64Target);
|
|
RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget);
|
|
}
|
|
|
|
// On function prologue, the stack is created by decrementing
|
|
// its pointer. Once decremented, all references are done with positive
|
|
// offset from the stack/frame pointer, using StackGrowsUp enables
|
|
// an easier handling.
|
|
// Using CodeModel::Large enables different CALL behavior.
|
|
MipsTargetMachine::MipsTargetMachine(const Target &T, StringRef TT,
|
|
StringRef CPU, StringRef FS,
|
|
const TargetOptions &Options,
|
|
Reloc::Model RM, CodeModel::Model CM,
|
|
CodeGenOpt::Level OL, bool isLittle)
|
|
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
|
|
isLittle(isLittle), Subtarget(nullptr),
|
|
DefaultSubtarget(TT, CPU, FS, isLittle, this),
|
|
NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
|
|
isLittle, this),
|
|
Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
|
|
isLittle, this) {
|
|
Subtarget = &DefaultSubtarget;
|
|
initAsmInfo();
|
|
}
|
|
|
|
void MipsebTargetMachine::anchor() { }
|
|
|
|
MipsebTargetMachine::
|
|
MipsebTargetMachine(const Target &T, StringRef TT,
|
|
StringRef CPU, StringRef FS, const TargetOptions &Options,
|
|
Reloc::Model RM, CodeModel::Model CM,
|
|
CodeGenOpt::Level OL)
|
|
: MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
|
|
|
|
void MipselTargetMachine::anchor() { }
|
|
|
|
MipselTargetMachine::
|
|
MipselTargetMachine(const Target &T, StringRef TT,
|
|
StringRef CPU, StringRef FS, const TargetOptions &Options,
|
|
Reloc::Model RM, CodeModel::Model CM,
|
|
CodeGenOpt::Level OL)
|
|
: MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
|
|
|
|
const MipsSubtarget *
|
|
MipsTargetMachine::getSubtargetImpl(const Function &F) const {
|
|
AttributeSet FnAttrs = F.getAttributes();
|
|
Attribute CPUAttr =
|
|
FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
|
|
Attribute FSAttr =
|
|
FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
|
|
|
|
std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
|
|
? CPUAttr.getValueAsString().str()
|
|
: TargetCPU;
|
|
std::string FS = !FSAttr.hasAttribute(Attribute::None)
|
|
? FSAttr.getValueAsString().str()
|
|
: TargetFS;
|
|
bool hasMips16Attr =
|
|
!FnAttrs.getAttribute(AttributeSet::FunctionIndex, "mips16")
|
|
.hasAttribute(Attribute::None);
|
|
bool hasNoMips16Attr =
|
|
!FnAttrs.getAttribute(AttributeSet::FunctionIndex, "nomips16")
|
|
.hasAttribute(Attribute::None);
|
|
|
|
// FIXME: This is related to the code below to reset the target options,
|
|
// we need to know whether or not the soft float flag is set on the
|
|
// function before we can generate a subtarget. We also need to use
|
|
// it as a key for the subtarget since that can be the only difference
|
|
// between two functions.
|
|
Attribute SFAttr =
|
|
FnAttrs.getAttribute(AttributeSet::FunctionIndex, "use-soft-float");
|
|
bool softFloat = !SFAttr.hasAttribute(Attribute::None)
|
|
? SFAttr.getValueAsString() == "true"
|
|
: Options.UseSoftFloat;
|
|
|
|
if (hasMips16Attr)
|
|
FS += FS.empty() ? "+mips16" : ",+mips16";
|
|
else if (hasNoMips16Attr)
|
|
FS += FS.empty() ? "-mips16" : ",-mips16";
|
|
|
|
auto &I = SubtargetMap[CPU + FS + (softFloat ? "use-soft-float=true"
|
|
: "use-soft-float=false")];
|
|
if (!I) {
|
|
// This needs to be done before we create a new subtarget since any
|
|
// creation will depend on the TM and the code generation flags on the
|
|
// function that reside in TargetOptions.
|
|
resetTargetOptions(F);
|
|
I = llvm::make_unique<MipsSubtarget>(TargetTriple, CPU, FS, isLittle, this);
|
|
}
|
|
return I.get();
|
|
}
|
|
|
|
void MipsTargetMachine::resetSubtarget(MachineFunction *MF) {
|
|
DEBUG(dbgs() << "resetSubtarget\n");
|
|
|
|
Subtarget = const_cast<MipsSubtarget *>(getSubtargetImpl(*MF->getFunction()));
|
|
MF->setSubtarget(Subtarget);
|
|
return;
|
|
}
|
|
|
|
namespace {
|
|
/// Mips Code Generator Pass Configuration Options.
|
|
class MipsPassConfig : public TargetPassConfig {
|
|
public:
|
|
MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
|
|
: TargetPassConfig(TM, PM) {
|
|
// The current implementation of long branch pass requires a scratch
|
|
// register ($at) to be available before branch instructions. Tail merging
|
|
// can break this requirement, so disable it when long branch pass is
|
|
// enabled.
|
|
EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
|
|
}
|
|
|
|
MipsTargetMachine &getMipsTargetMachine() const {
|
|
return getTM<MipsTargetMachine>();
|
|
}
|
|
|
|
const MipsSubtarget &getMipsSubtarget() const {
|
|
return *getMipsTargetMachine().getSubtargetImpl();
|
|
}
|
|
|
|
void addIRPasses() override;
|
|
bool addInstSelector() override;
|
|
void addMachineSSAOptimization() override;
|
|
bool addPreEmitPass() override;
|
|
|
|
bool addPreRegAlloc() override;
|
|
|
|
};
|
|
} // namespace
|
|
|
|
TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
|
|
return new MipsPassConfig(this, PM);
|
|
}
|
|
|
|
void MipsPassConfig::addIRPasses() {
|
|
TargetPassConfig::addIRPasses();
|
|
addPass(createAtomicExpandPass(&getMipsTargetMachine()));
|
|
if (getMipsSubtarget().os16())
|
|
addPass(createMipsOs16(getMipsTargetMachine()));
|
|
if (getMipsSubtarget().inMips16HardFloat())
|
|
addPass(createMips16HardFloat(getMipsTargetMachine()));
|
|
}
|
|
// Install an instruction selector pass using
|
|
// the ISelDag to gen Mips code.
|
|
bool MipsPassConfig::addInstSelector() {
|
|
addPass(createMipsModuleISelDag(getMipsTargetMachine()));
|
|
addPass(createMips16ISelDag(getMipsTargetMachine()));
|
|
addPass(createMipsSEISelDag(getMipsTargetMachine()));
|
|
return false;
|
|
}
|
|
|
|
void MipsPassConfig::addMachineSSAOptimization() {
|
|
addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
|
|
TargetPassConfig::addMachineSSAOptimization();
|
|
}
|
|
|
|
bool MipsPassConfig::addPreRegAlloc() {
|
|
if (getOptLevel() == CodeGenOpt::None) {
|
|
addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
|
|
return true;
|
|
}
|
|
else
|
|
return false;
|
|
}
|
|
|
|
void MipsTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
|
|
if (Subtarget->allowMixed16_32()) {
|
|
DEBUG(errs() << "No ");
|
|
//FIXME: The Basic Target Transform Info
|
|
// pass needs to become a function pass instead of
|
|
// being an immutable pass and then this method as it exists now
|
|
// would be unnecessary.
|
|
PM.add(createNoTargetTransformInfoPass());
|
|
} else
|
|
LLVMTargetMachine::addAnalysisPasses(PM);
|
|
DEBUG(errs() << "Target Transform Info Pass Added\n");
|
|
}
|
|
|
|
// Implemented by targets that want to run passes immediately before
|
|
// machine code is emitted. return true if -print-machineinstrs should
|
|
// print out the code after the passes.
|
|
bool MipsPassConfig::addPreEmitPass() {
|
|
MipsTargetMachine &TM = getMipsTargetMachine();
|
|
addPass(createMipsDelaySlotFillerPass(TM));
|
|
addPass(createMipsLongBranchPass(TM));
|
|
addPass(createMipsConstantIslandPass(TM));
|
|
return true;
|
|
}
|