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2c3a4641a7
Mips16 is really a processor decoding mode (ala thumb 1) and in the same program, mips16 and mips32 functions can exist and can call each other. If a jal type instruction encounters an address with the lower bit set, then the processor switches to mips16 mode (if it is not already in it). If the lower bit is not set, then it switches to mips32 mode. The linker knows which functions are mips16 and which are mips32. When relocation is performed on code labels, this lower order bit is set if the code label is a mips16 code label. In general this works just fine, however when creating exception handling tables and dwarf, there are cases where you don't want this lower order bit added in. This has been traditionally distinguished in gas assembly source by using a different syntax for the label. lab1: ; this will cause the lower order bit to be added lab2=. ; this will not cause the lower order bit to be added In some cases, it does not matter because in dwarf and debug tables the difference of two labels is used and in that case the lower order bits subtract each other out. To fix this, I have added to mcstreamer the notion of a debuglabel. The default is for label and debug label to be the same. So calling EmitLabel and EmitDebugLabel produce the same result. For various reasons, there is only one set of labels that needs to be modified for the mips exceptions to work. These are the "$eh_func_beginXXX" labels. Mips overrides the debug label suffix from ":" to "=." . This initial patch fixes exceptions. More changes most likely will be needed to DwarfCFException to make all of this work for actual debugging. These changes will be to emit debug labels in some places where a simple label is emitted now. Some historical discussion on this from gcc can be found at: http://gcc.gnu.org/ml/gcc-patches/2008-08/msg00623.html http://gcc.gnu.org/ml/gcc-patches/2008-11/msg01273.html git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170279 91177308-0d34-0410-b5e6-96231b3b80d8
88 lines
3.2 KiB
LLVM
88 lines
3.2 KiB
LLVM
; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
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;16: $eh_func_begin0=.
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@.str = private unnamed_addr constant [7 x i8] c"hello\0A\00", align 1
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@_ZTIi = external constant i8*
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@.str1 = private unnamed_addr constant [15 x i8] c"exception %i \0A\00", align 1
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define i32 @main() {
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entry:
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%retval = alloca i32, align 4
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%exn.slot = alloca i8*
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%ehselector.slot = alloca i32
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%e = alloca i32, align 4
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store i32 0, i32* %retval
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%call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0))
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%exception = call i8* @__cxa_allocate_exception(i32 4) nounwind
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%0 = bitcast i8* %exception to i32*
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store i32 20, i32* %0
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invoke void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIi to i8*), i8* null) noreturn
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to label %unreachable unwind label %lpad
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lpad: ; preds = %entry
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%1 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
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catch i8* bitcast (i8** @_ZTIi to i8*)
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%2 = extractvalue { i8*, i32 } %1, 0
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store i8* %2, i8** %exn.slot
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%3 = extractvalue { i8*, i32 } %1, 1
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store i32 %3, i32* %ehselector.slot
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br label %catch.dispatch
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catch.dispatch: ; preds = %lpad
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%sel = load i32* %ehselector.slot
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%4 = call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*)) nounwind
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%matches = icmp eq i32 %sel, %4
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br i1 %matches, label %catch, label %eh.resume
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catch: ; preds = %catch.dispatch
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%exn = load i8** %exn.slot
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%5 = call i8* @__cxa_begin_catch(i8* %exn) nounwind
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%6 = bitcast i8* %5 to i32*
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%exn.scalar = load i32* %6
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store i32 %exn.scalar, i32* %e, align 4
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%7 = load i32* %e, align 4
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%call2 = invoke i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([15 x i8]* @.str1, i32 0, i32 0), i32 %7)
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to label %invoke.cont unwind label %lpad1
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invoke.cont: ; preds = %catch
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call void @__cxa_end_catch() nounwind
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br label %try.cont
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try.cont: ; preds = %invoke.cont
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ret i32 0
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lpad1: ; preds = %catch
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%8 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
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cleanup
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%9 = extractvalue { i8*, i32 } %8, 0
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store i8* %9, i8** %exn.slot
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%10 = extractvalue { i8*, i32 } %8, 1
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store i32 %10, i32* %ehselector.slot
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call void @__cxa_end_catch() nounwind
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br label %eh.resume
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eh.resume: ; preds = %lpad1, %catch.dispatch
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%exn3 = load i8** %exn.slot
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%sel4 = load i32* %ehselector.slot
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%lpad.val = insertvalue { i8*, i32 } undef, i8* %exn3, 0
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%lpad.val5 = insertvalue { i8*, i32 } %lpad.val, i32 %sel4, 1
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resume { i8*, i32 } %lpad.val5
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unreachable: ; preds = %entry
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unreachable
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}
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declare i32 @printf(i8*, ...)
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declare i8* @__cxa_allocate_exception(i32)
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declare i32 @__gxx_personality_v0(...)
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declare void @__cxa_throw(i8*, i8*, i8*)
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declare i32 @llvm.eh.typeid.for(i8*) nounwind readnone
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declare i8* @__cxa_begin_catch(i8*)
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declare void @__cxa_end_catch()
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