Daniel Sanders 67db74e02c [mips] Implement shorthand add / sub forms for MIPS. ... Summary: - If only two registers are passed to a three-register operation, then the first argument is both source and destination register. - If a non-register is passed as the last argument, generate the immediate version of the instruction. Also mark DADD commutative and add scheduling information (to the generic scheduler), and implement DSUB. Patch by David Chisnall His work was sponsored by: DARPA, AFRL CC: theraven Differential Revision: http://llvm-reviews.chandlerc.com/D3148 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204605 91177308-0d34-0410-b5e6-96231b3b80d8		2014-03-24 14:05:39 +00:00
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AArch64
ARM	Teach llvm-readobj to print human friendly description of reserved sections.	2014-03-24 05:00:34 +00:00
AsmParser
COFF
Disassembler	[SystemZ] Add support for z196 float<->unsigned conversions	2014-03-21 10:56:30 +00:00
ELF	Teach llvm-readobj to print human friendly description of reserved sections.	2014-03-24 05:00:34 +00:00
MachO	Move codegen test over to MC.	2014-03-21 17:55:34 +00:00
Markup
Mips	[mips] Implement shorthand add / sub forms for MIPS.	2014-03-24 14:05:39 +00:00
PowerPC
Sparc
SystemZ	[SystemZ] Add support for z196 float<->unsigned conversions	2014-03-21 10:56:30 +00:00
X86