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This reverts commit r200058 and adds the using directive for ARMTargetTransformInfo to silence two g++ overload warnings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200062 91177308-0d34-0410-b5e6-96231b3b80d8
779 lines
30 KiB
C++
779 lines
30 KiB
C++
//===-- Passes.cpp - Target independent code generation passes ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines interfaces to access the target independent code
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// generation passes provided by the LLVM backend.
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//
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//===---------------------------------------------------------------------===//
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Analysis/Passes.h"
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#include "llvm/CodeGen/GCStrategy.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/IR/IRPrintingPasses.h"
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#include "llvm/IR/Verifier.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include "llvm/Transforms/Scalar.h"
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using namespace llvm;
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namespace llvm {
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extern cl::opt<bool> EnableStackMapLiveness;
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extern cl::opt<bool> EnablePatchPointLiveness;
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}
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static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
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cl::desc("Disable Post Regalloc"));
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static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
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cl::desc("Disable branch folding"));
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static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
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cl::desc("Disable tail duplication"));
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static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
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cl::desc("Disable pre-register allocation tail duplication"));
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static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
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cl::Hidden, cl::desc("Disable probability-driven block placement"));
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static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
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cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
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static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
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cl::desc("Disable Stack Slot Coloring"));
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static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
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cl::desc("Disable Machine Dead Code Elimination"));
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static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
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cl::desc("Disable Early If-conversion"));
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static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
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cl::desc("Disable Machine LICM"));
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static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
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cl::desc("Disable Machine Common Subexpression Elimination"));
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static cl::opt<cl::boolOrDefault>
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OptimizeRegAlloc("optimize-regalloc", cl::Hidden,
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cl::desc("Enable optimized register allocation compilation path."));
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static cl::opt<cl::boolOrDefault>
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EnableMachineSched("enable-misched",
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cl::desc("Enable the machine instruction scheduling pass."));
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static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
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cl::Hidden,
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cl::desc("Disable Machine LICM"));
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static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
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cl::desc("Disable Machine Sinking"));
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static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
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cl::desc("Disable Loop Strength Reduction Pass"));
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static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
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cl::Hidden, cl::desc("Disable ConstantHoisting"));
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static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
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cl::desc("Disable Codegen Prepare"));
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static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
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cl::desc("Disable Copy Propagation pass"));
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static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
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cl::desc("Print LLVM IR produced by the loop-reduce pass"));
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static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
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cl::desc("Print LLVM IR input to isel pass"));
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static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
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cl::desc("Dump garbage collector data"));
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static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
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cl::desc("Verify generated machine code"),
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cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
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static cl::opt<std::string>
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PrintMachineInstrs("print-machineinstrs", cl::ValueOptional,
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cl::desc("Print machine instrs"),
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cl::value_desc("pass-name"), cl::init("option-unspecified"));
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// Temporary option to allow experimenting with MachineScheduler as a post-RA
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// scheduler. Targets can "properly" enable this with
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// substitutePass(&PostRASchedulerID, &MachineSchedulerID); Ideally it wouldn't
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// be part of the standard pass pipeline, and the target would just add a PostRA
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// scheduling pass wherever it wants.
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static cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
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cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
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// Experimental option to run live interval analysis early.
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static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
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cl::desc("Run live interval analysis earlier in the pipeline"));
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/// Allow standard passes to be disabled by command line options. This supports
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/// simple binary flags that either suppress the pass or do nothing.
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/// i.e. -disable-mypass=false has no effect.
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/// These should be converted to boolOrDefault in order to use applyOverride.
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static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID,
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bool Override) {
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if (Override)
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return IdentifyingPassPtr();
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return PassID;
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}
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/// Allow Pass selection to be overriden by command line options. This supports
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/// flags with ternary conditions. TargetID is passed through by default. The
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/// pass is suppressed when the option is false. When the option is true, the
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/// StandardID is selected if the target provides no default.
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static IdentifyingPassPtr applyOverride(IdentifyingPassPtr TargetID,
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cl::boolOrDefault Override,
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AnalysisID StandardID) {
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switch (Override) {
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case cl::BOU_UNSET:
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return TargetID;
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case cl::BOU_TRUE:
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if (TargetID.isValid())
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return TargetID;
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if (StandardID == 0)
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report_fatal_error("Target cannot enable pass");
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return StandardID;
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case cl::BOU_FALSE:
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return IdentifyingPassPtr();
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}
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llvm_unreachable("Invalid command line option state");
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}
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/// Allow standard passes to be disabled by the command line, regardless of who
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/// is adding the pass.
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///
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/// StandardID is the pass identified in the standard pass pipeline and provided
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/// to addPass(). It may be a target-specific ID in the case that the target
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/// directly adds its own pass, but in that case we harmlessly fall through.
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///
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/// TargetID is the pass that the target has configured to override StandardID.
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///
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/// StandardID may be a pseudo ID. In that case TargetID is the name of the real
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/// pass to run. This allows multiple options to control a single pass depending
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/// on where in the pipeline that pass is added.
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static IdentifyingPassPtr overridePass(AnalysisID StandardID,
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IdentifyingPassPtr TargetID) {
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if (StandardID == &PostRASchedulerID)
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return applyDisable(TargetID, DisablePostRA);
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if (StandardID == &BranchFolderPassID)
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return applyDisable(TargetID, DisableBranchFold);
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if (StandardID == &TailDuplicateID)
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return applyDisable(TargetID, DisableTailDuplicate);
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if (StandardID == &TargetPassConfig::EarlyTailDuplicateID)
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return applyDisable(TargetID, DisableEarlyTailDup);
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if (StandardID == &MachineBlockPlacementID)
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return applyDisable(TargetID, DisableBlockPlacement);
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if (StandardID == &StackSlotColoringID)
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return applyDisable(TargetID, DisableSSC);
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if (StandardID == &DeadMachineInstructionElimID)
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return applyDisable(TargetID, DisableMachineDCE);
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if (StandardID == &EarlyIfConverterID)
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return applyDisable(TargetID, DisableEarlyIfConversion);
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if (StandardID == &MachineLICMID)
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return applyDisable(TargetID, DisableMachineLICM);
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if (StandardID == &MachineCSEID)
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return applyDisable(TargetID, DisableMachineCSE);
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if (StandardID == &MachineSchedulerID)
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return applyOverride(TargetID, EnableMachineSched, StandardID);
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if (StandardID == &TargetPassConfig::PostRAMachineLICMID)
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return applyDisable(TargetID, DisablePostRAMachineLICM);
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if (StandardID == &MachineSinkingID)
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return applyDisable(TargetID, DisableMachineSink);
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if (StandardID == &MachineCopyPropagationID)
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return applyDisable(TargetID, DisableCopyProp);
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return TargetID;
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}
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//===---------------------------------------------------------------------===//
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/// TargetPassConfig
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//===---------------------------------------------------------------------===//
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INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
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"Target Pass Configuration", false, false)
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char TargetPassConfig::ID = 0;
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// Pseudo Pass IDs.
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char TargetPassConfig::EarlyTailDuplicateID = 0;
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char TargetPassConfig::PostRAMachineLICMID = 0;
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namespace llvm {
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class PassConfigImpl {
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public:
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// List of passes explicitly substituted by this target. Normally this is
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// empty, but it is a convenient way to suppress or replace specific passes
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// that are part of a standard pass pipeline without overridding the entire
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// pipeline. This mechanism allows target options to inherit a standard pass's
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// user interface. For example, a target may disable a standard pass by
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// default by substituting a pass ID of zero, and the user may still enable
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// that standard pass with an explicit command line option.
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DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses;
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/// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
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/// is inserted after each instance of the first one.
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SmallVector<std::pair<AnalysisID, IdentifyingPassPtr>, 4> InsertedPasses;
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};
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} // namespace llvm
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// Out of line virtual method.
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TargetPassConfig::~TargetPassConfig() {
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delete Impl;
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}
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// Out of line constructor provides default values for pass options and
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// registers all common codegen passes.
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TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
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: ImmutablePass(ID), PM(&pm), StartAfter(0), StopAfter(0),
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Started(true), Stopped(false), TM(tm), Impl(0), Initialized(false),
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DisableVerify(false),
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EnableTailMerge(true) {
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Impl = new PassConfigImpl();
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// Register all target independent codegen passes to activate their PassIDs,
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// including this pass itself.
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initializeCodeGen(*PassRegistry::getPassRegistry());
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// Substitute Pseudo Pass IDs for real ones.
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substitutePass(&EarlyTailDuplicateID, &TailDuplicateID);
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substitutePass(&PostRAMachineLICMID, &MachineLICMID);
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// Temporarily disable experimental passes.
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const TargetSubtargetInfo &ST = TM->getSubtarget<TargetSubtargetInfo>();
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if (!ST.useMachineScheduler())
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disablePass(&MachineSchedulerID);
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}
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/// Insert InsertedPassID pass after TargetPassID.
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void TargetPassConfig::insertPass(AnalysisID TargetPassID,
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IdentifyingPassPtr InsertedPassID) {
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assert(((!InsertedPassID.isInstance() &&
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TargetPassID != InsertedPassID.getID()) ||
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(InsertedPassID.isInstance() &&
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TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
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"Insert a pass after itself!");
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std::pair<AnalysisID, IdentifyingPassPtr> P(TargetPassID, InsertedPassID);
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Impl->InsertedPasses.push_back(P);
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}
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/// createPassConfig - Create a pass configuration object to be used by
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/// addPassToEmitX methods for generating a pipeline of CodeGen passes.
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///
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/// Targets may override this to extend TargetPassConfig.
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TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new TargetPassConfig(this, PM);
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}
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TargetPassConfig::TargetPassConfig()
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: ImmutablePass(ID), PM(0) {
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llvm_unreachable("TargetPassConfig should not be constructed on-the-fly");
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}
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// Helper to verify the analysis is really immutable.
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void TargetPassConfig::setOpt(bool &Opt, bool Val) {
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assert(!Initialized && "PassConfig is immutable");
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Opt = Val;
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}
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void TargetPassConfig::substitutePass(AnalysisID StandardID,
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IdentifyingPassPtr TargetID) {
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Impl->TargetPasses[StandardID] = TargetID;
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}
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IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
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DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator
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I = Impl->TargetPasses.find(ID);
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if (I == Impl->TargetPasses.end())
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return ID;
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return I->second;
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}
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/// Add a pass to the PassManager if that pass is supposed to be run. If the
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/// Started/Stopped flags indicate either that the compilation should start at
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/// a later pass or that it should stop after an earlier pass, then do not add
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/// the pass. Finally, compare the current pass against the StartAfter
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/// and StopAfter options and change the Started/Stopped flags accordingly.
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void TargetPassConfig::addPass(Pass *P) {
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assert(!Initialized && "PassConfig is immutable");
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// Cache the Pass ID here in case the pass manager finds this pass is
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// redundant with ones already scheduled / available, and deletes it.
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// Fundamentally, once we add the pass to the manager, we no longer own it
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// and shouldn't reference it.
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AnalysisID PassID = P->getPassID();
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if (Started && !Stopped)
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PM->add(P);
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else
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delete P;
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if (StopAfter == PassID)
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Stopped = true;
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if (StartAfter == PassID)
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Started = true;
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if (Stopped && !Started)
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report_fatal_error("Cannot stop compilation after pass that is not run");
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}
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/// Add a CodeGen pass at this point in the pipeline after checking for target
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/// and command line overrides.
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///
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/// addPass cannot return a pointer to the pass instance because is internal the
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/// PassManager and the instance we create here may already be freed.
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AnalysisID TargetPassConfig::addPass(AnalysisID PassID) {
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IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
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IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
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if (!FinalPtr.isValid())
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return 0;
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Pass *P;
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if (FinalPtr.isInstance())
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P = FinalPtr.getInstance();
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else {
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P = Pass::createPass(FinalPtr.getID());
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if (!P)
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llvm_unreachable("Pass ID not registered");
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}
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AnalysisID FinalID = P->getPassID();
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addPass(P); // Ends the lifetime of P.
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// Add the passes after the pass P if there is any.
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for (SmallVectorImpl<std::pair<AnalysisID, IdentifyingPassPtr> >::iterator
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I = Impl->InsertedPasses.begin(), E = Impl->InsertedPasses.end();
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I != E; ++I) {
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if ((*I).first == PassID) {
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assert((*I).second.isValid() && "Illegal Pass ID!");
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Pass *NP;
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if ((*I).second.isInstance())
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NP = (*I).second.getInstance();
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else {
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NP = Pass::createPass((*I).second.getID());
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assert(NP && "Pass ID not registered");
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}
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addPass(NP);
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}
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}
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return FinalID;
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}
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void TargetPassConfig::printAndVerify(const char *Banner) {
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if (TM->shouldPrintMachineCode())
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addPass(createMachineFunctionPrinterPass(dbgs(), Banner));
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if (VerifyMachineCode)
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addPass(createMachineVerifierPass(Banner));
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}
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/// Add common target configurable passes that perform LLVM IR to IR transforms
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/// following machine independent optimization.
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void TargetPassConfig::addIRPasses() {
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// Basic AliasAnalysis support.
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// Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
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// BasicAliasAnalysis wins if they disagree. This is intended to help
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// support "obvious" type-punning idioms.
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addPass(createTypeBasedAliasAnalysisPass());
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addPass(createBasicAliasAnalysisPass());
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// Before running any passes, run the verifier to determine if the input
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// coming from the front-end and/or optimizer is valid.
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if (!DisableVerify)
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addPass(createVerifierPass());
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// Run loop strength reduction before anything else.
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if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
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addPass(createLoopStrengthReducePass());
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if (PrintLSR)
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addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
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}
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addPass(createGCLoweringPass());
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// Make sure that no unreachable blocks are instruction selected.
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addPass(createUnreachableBlockEliminationPass());
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// Prepare expensive constants for SelectionDAG.
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if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting)
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addPass(createConstantHoistingPass());
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}
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/// Turn exception handling constructs into something the code generators can
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/// handle.
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void TargetPassConfig::addPassesToHandleExceptions() {
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switch (TM->getMCAsmInfo()->getExceptionHandlingType()) {
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case ExceptionHandling::SjLj:
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// SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
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// Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
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// catch info can get misplaced when a selector ends up more than one block
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// removed from the parent invoke(s). This could happen when a landing
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// pad is shared by multiple invokes and is also a target of a normal
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// edge from elsewhere.
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addPass(createSjLjEHPreparePass(TM));
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// FALLTHROUGH
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case ExceptionHandling::DwarfCFI:
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case ExceptionHandling::ARM:
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case ExceptionHandling::Win64:
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addPass(createDwarfEHPass(TM));
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break;
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case ExceptionHandling::None:
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addPass(createLowerInvokePass(TM));
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// The lower invoke pass may create unreachable code. Remove it.
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addPass(createUnreachableBlockEliminationPass());
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break;
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}
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}
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/// Add pass to prepare the LLVM IR for code generation. This should be done
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/// before exception handling preparation passes.
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void TargetPassConfig::addCodeGenPrepare() {
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if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
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addPass(createCodeGenPreparePass(TM));
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}
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/// Add common passes that perform LLVM IR to IR transforms in preparation for
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/// instruction selection.
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void TargetPassConfig::addISelPrepare() {
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addPreISel();
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addPass(createStackProtectorPass(TM));
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if (PrintISelInput)
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addPass(createPrintFunctionPass(
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dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
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// All passes which modify the LLVM IR are now complete; run the verifier
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// to ensure that the IR is valid.
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if (!DisableVerify)
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addPass(createVerifierPass());
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}
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/// Add the complete set of target-independent postISel code generator passes.
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///
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/// This can be read as the standard order of major LLVM CodeGen stages. Stages
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/// with nontrivial configuration or multiple passes are broken out below in
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/// add%Stage routines.
|
|
///
|
|
/// Any TargetPassConfig::addXX routine may be overriden by the Target. The
|
|
/// addPre/Post methods with empty header implementations allow injecting
|
|
/// target-specific fixups just before or after major stages. Additionally,
|
|
/// targets have the flexibility to change pass order within a stage by
|
|
/// overriding default implementation of add%Stage routines below. Each
|
|
/// technique has maintainability tradeoffs because alternate pass orders are
|
|
/// not well supported. addPre/Post works better if the target pass is easily
|
|
/// tied to a common pass. But if it has subtle dependencies on multiple passes,
|
|
/// the target should override the stage instead.
|
|
///
|
|
/// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
|
|
/// before/after any target-independent pass. But it's currently overkill.
|
|
void TargetPassConfig::addMachinePasses() {
|
|
// Insert a machine instr printer pass after the specified pass.
|
|
// If -print-machineinstrs specified, print machineinstrs after all passes.
|
|
if (StringRef(PrintMachineInstrs.getValue()).equals(""))
|
|
TM->Options.PrintMachineCode = true;
|
|
else if (!StringRef(PrintMachineInstrs.getValue())
|
|
.equals("option-unspecified")) {
|
|
const PassRegistry *PR = PassRegistry::getPassRegistry();
|
|
const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue());
|
|
const PassInfo *IPI = PR->getPassInfo(StringRef("print-machineinstrs"));
|
|
assert (TPI && IPI && "Pass ID not registered!");
|
|
const char *TID = (const char *)(TPI->getTypeInfo());
|
|
const char *IID = (const char *)(IPI->getTypeInfo());
|
|
insertPass(TID, IID);
|
|
}
|
|
|
|
// Print the instruction selected machine code...
|
|
printAndVerify("After Instruction Selection");
|
|
|
|
// Expand pseudo-instructions emitted by ISel.
|
|
if (addPass(&ExpandISelPseudosID))
|
|
printAndVerify("After ExpandISelPseudos");
|
|
|
|
// Add passes that optimize machine instructions in SSA form.
|
|
if (getOptLevel() != CodeGenOpt::None) {
|
|
addMachineSSAOptimization();
|
|
} else {
|
|
// If the target requests it, assign local variables to stack slots relative
|
|
// to one another and simplify frame index references where possible.
|
|
addPass(&LocalStackSlotAllocationID);
|
|
}
|
|
|
|
// Run pre-ra passes.
|
|
if (addPreRegAlloc())
|
|
printAndVerify("After PreRegAlloc passes");
|
|
|
|
// Run register allocation and passes that are tightly coupled with it,
|
|
// including phi elimination and scheduling.
|
|
if (getOptimizeRegAlloc())
|
|
addOptimizedRegAlloc(createRegAllocPass(true));
|
|
else
|
|
addFastRegAlloc(createRegAllocPass(false));
|
|
|
|
// Run post-ra passes.
|
|
if (addPostRegAlloc())
|
|
printAndVerify("After PostRegAlloc passes");
|
|
|
|
// Insert prolog/epilog code. Eliminate abstract frame index references...
|
|
addPass(&PrologEpilogCodeInserterID);
|
|
printAndVerify("After PrologEpilogCodeInserter");
|
|
|
|
/// Add passes that optimize machine instructions after register allocation.
|
|
if (getOptLevel() != CodeGenOpt::None)
|
|
addMachineLateOptimization();
|
|
|
|
// Expand pseudo instructions before second scheduling pass.
|
|
addPass(&ExpandPostRAPseudosID);
|
|
printAndVerify("After ExpandPostRAPseudos");
|
|
|
|
// Run pre-sched2 passes.
|
|
if (addPreSched2())
|
|
printAndVerify("After PreSched2 passes");
|
|
|
|
// Second pass scheduler.
|
|
if (getOptLevel() != CodeGenOpt::None) {
|
|
if (MISchedPostRA)
|
|
addPass(&PostMachineSchedulerID);
|
|
else
|
|
addPass(&PostRASchedulerID);
|
|
printAndVerify("After PostRAScheduler");
|
|
}
|
|
|
|
// GC
|
|
if (addGCPasses()) {
|
|
if (PrintGCInfo)
|
|
addPass(createGCInfoPrinter(dbgs()));
|
|
}
|
|
|
|
// Basic block placement.
|
|
if (getOptLevel() != CodeGenOpt::None)
|
|
addBlockPlacement();
|
|
|
|
if (addPreEmitPass())
|
|
printAndVerify("After PreEmit passes");
|
|
|
|
if (EnableStackMapLiveness || EnablePatchPointLiveness)
|
|
addPass(&StackMapLivenessID);
|
|
}
|
|
|
|
/// Add passes that optimize machine instructions in SSA form.
|
|
void TargetPassConfig::addMachineSSAOptimization() {
|
|
// Pre-ra tail duplication.
|
|
if (addPass(&EarlyTailDuplicateID))
|
|
printAndVerify("After Pre-RegAlloc TailDuplicate");
|
|
|
|
// Optimize PHIs before DCE: removing dead PHI cycles may make more
|
|
// instructions dead.
|
|
addPass(&OptimizePHIsID);
|
|
|
|
// This pass merges large allocas. StackSlotColoring is a different pass
|
|
// which merges spill slots.
|
|
addPass(&StackColoringID);
|
|
|
|
// If the target requests it, assign local variables to stack slots relative
|
|
// to one another and simplify frame index references where possible.
|
|
addPass(&LocalStackSlotAllocationID);
|
|
|
|
// With optimization, dead code should already be eliminated. However
|
|
// there is one known exception: lowered code for arguments that are only
|
|
// used by tail calls, where the tail calls reuse the incoming stack
|
|
// arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
|
|
addPass(&DeadMachineInstructionElimID);
|
|
printAndVerify("After codegen DCE pass");
|
|
|
|
// Allow targets to insert passes that improve instruction level parallelism,
|
|
// like if-conversion. Such passes will typically need dominator trees and
|
|
// loop info, just like LICM and CSE below.
|
|
if (addILPOpts())
|
|
printAndVerify("After ILP optimizations");
|
|
|
|
addPass(&MachineLICMID);
|
|
addPass(&MachineCSEID);
|
|
addPass(&MachineSinkingID);
|
|
printAndVerify("After Machine LICM, CSE and Sinking passes");
|
|
|
|
addPass(&PeepholeOptimizerID);
|
|
printAndVerify("After codegen peephole optimization pass");
|
|
}
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
/// Register Allocation Pass Configuration
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
bool TargetPassConfig::getOptimizeRegAlloc() const {
|
|
switch (OptimizeRegAlloc) {
|
|
case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
|
|
case cl::BOU_TRUE: return true;
|
|
case cl::BOU_FALSE: return false;
|
|
}
|
|
llvm_unreachable("Invalid optimize-regalloc state");
|
|
}
|
|
|
|
/// RegisterRegAlloc's global Registry tracks allocator registration.
|
|
MachinePassRegistry RegisterRegAlloc::Registry;
|
|
|
|
/// A dummy default pass factory indicates whether the register allocator is
|
|
/// overridden on the command line.
|
|
static FunctionPass *useDefaultRegisterAllocator() { return 0; }
|
|
static RegisterRegAlloc
|
|
defaultRegAlloc("default",
|
|
"pick register allocator based on -O option",
|
|
useDefaultRegisterAllocator);
|
|
|
|
/// -regalloc=... command line option.
|
|
static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
|
|
RegisterPassParser<RegisterRegAlloc> >
|
|
RegAlloc("regalloc",
|
|
cl::init(&useDefaultRegisterAllocator),
|
|
cl::desc("Register allocator to use"));
|
|
|
|
|
|
/// Instantiate the default register allocator pass for this target for either
|
|
/// the optimized or unoptimized allocation path. This will be added to the pass
|
|
/// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
|
|
/// in the optimized case.
|
|
///
|
|
/// A target that uses the standard regalloc pass order for fast or optimized
|
|
/// allocation may still override this for per-target regalloc
|
|
/// selection. But -regalloc=... always takes precedence.
|
|
FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) {
|
|
if (Optimized)
|
|
return createGreedyRegisterAllocator();
|
|
else
|
|
return createFastRegisterAllocator();
|
|
}
|
|
|
|
/// Find and instantiate the register allocation pass requested by this target
|
|
/// at the current optimization level. Different register allocators are
|
|
/// defined as separate passes because they may require different analysis.
|
|
///
|
|
/// This helper ensures that the regalloc= option is always available,
|
|
/// even for targets that override the default allocator.
|
|
///
|
|
/// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
|
|
/// this can be folded into addPass.
|
|
FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
|
|
RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
|
|
|
|
// Initialize the global default.
|
|
if (!Ctor) {
|
|
Ctor = RegAlloc;
|
|
RegisterRegAlloc::setDefault(RegAlloc);
|
|
}
|
|
if (Ctor != useDefaultRegisterAllocator)
|
|
return Ctor();
|
|
|
|
// With no -regalloc= override, ask the target for a regalloc pass.
|
|
return createTargetRegisterAllocator(Optimized);
|
|
}
|
|
|
|
/// Add the minimum set of target-independent passes that are required for
|
|
/// register allocation. No coalescing or scheduling.
|
|
void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
|
|
addPass(&PHIEliminationID);
|
|
addPass(&TwoAddressInstructionPassID);
|
|
|
|
addPass(RegAllocPass);
|
|
printAndVerify("After Register Allocation");
|
|
}
|
|
|
|
/// Add standard target-independent passes that are tightly coupled with
|
|
/// optimized register allocation, including coalescing, machine instruction
|
|
/// scheduling, and register allocation itself.
|
|
void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
|
|
addPass(&ProcessImplicitDefsID);
|
|
|
|
// LiveVariables currently requires pure SSA form.
|
|
//
|
|
// FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
|
|
// LiveVariables can be removed completely, and LiveIntervals can be directly
|
|
// computed. (We still either need to regenerate kill flags after regalloc, or
|
|
// preferably fix the scavenger to not depend on them).
|
|
addPass(&LiveVariablesID);
|
|
|
|
// Edge splitting is smarter with machine loop info.
|
|
addPass(&MachineLoopInfoID);
|
|
addPass(&PHIEliminationID);
|
|
|
|
// Eventually, we want to run LiveIntervals before PHI elimination.
|
|
if (EarlyLiveIntervals)
|
|
addPass(&LiveIntervalsID);
|
|
|
|
addPass(&TwoAddressInstructionPassID);
|
|
addPass(&RegisterCoalescerID);
|
|
|
|
// PreRA instruction scheduling.
|
|
if (addPass(&MachineSchedulerID))
|
|
printAndVerify("After Machine Scheduling");
|
|
|
|
// Add the selected register allocation pass.
|
|
addPass(RegAllocPass);
|
|
printAndVerify("After Register Allocation, before rewriter");
|
|
|
|
// Allow targets to change the register assignments before rewriting.
|
|
if (addPreRewrite())
|
|
printAndVerify("After pre-rewrite passes");
|
|
|
|
// Finally rewrite virtual registers.
|
|
addPass(&VirtRegRewriterID);
|
|
printAndVerify("After Virtual Register Rewriter");
|
|
|
|
// Perform stack slot coloring and post-ra machine LICM.
|
|
//
|
|
// FIXME: Re-enable coloring with register when it's capable of adding
|
|
// kill markers.
|
|
addPass(&StackSlotColoringID);
|
|
|
|
// Run post-ra machine LICM to hoist reloads / remats.
|
|
//
|
|
// FIXME: can this move into MachineLateOptimization?
|
|
addPass(&PostRAMachineLICMID);
|
|
|
|
printAndVerify("After StackSlotColoring and postra Machine LICM");
|
|
}
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
/// Post RegAlloc Pass Configuration
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
/// Add passes that optimize machine instructions after register allocation.
|
|
void TargetPassConfig::addMachineLateOptimization() {
|
|
// Branch folding must be run after regalloc and prolog/epilog insertion.
|
|
if (addPass(&BranchFolderPassID))
|
|
printAndVerify("After BranchFolding");
|
|
|
|
// Tail duplication.
|
|
// Note that duplicating tail just increases code size and degrades
|
|
// performance for targets that require Structured Control Flow.
|
|
// In addition it can also make CFG irreducible. Thus we disable it.
|
|
if (!TM->requiresStructuredCFG() && addPass(&TailDuplicateID))
|
|
printAndVerify("After TailDuplicate");
|
|
|
|
// Copy propagation.
|
|
if (addPass(&MachineCopyPropagationID))
|
|
printAndVerify("After copy propagation pass");
|
|
}
|
|
|
|
/// Add standard GC passes.
|
|
bool TargetPassConfig::addGCPasses() {
|
|
addPass(&GCMachineCodeAnalysisID);
|
|
return true;
|
|
}
|
|
|
|
/// Add standard basic block placement passes.
|
|
void TargetPassConfig::addBlockPlacement() {
|
|
if (addPass(&MachineBlockPlacementID)) {
|
|
// Run a separate pass to collect block placement statistics.
|
|
if (EnableBlockPlacementStats)
|
|
addPass(&MachineBlockPlacementStatsID);
|
|
|
|
printAndVerify("After machine block placement.");
|
|
}
|
|
}
|