mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-24 23:29:41 +00:00
49683f3c96
The new target machines are: nvptx (old ptx32) => 32-bit PTX nvptx64 (old ptx64) => 64-bit PTX The sources are based on the internal NVIDIA NVPTX back-end, and contain more functionality than the current PTX back-end currently provides. NV_CONTRIB git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156196 91177308-0d34-0410-b5e6-96231b3b80d8
203 lines
7.8 KiB
Python
203 lines
7.8 KiB
Python
#!/usr/bin/env python
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num_regs = 396
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outFile = open('NVPTXRegisterInfo.td', 'w')
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outFile.write('''
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//===-- NVPTXRegisterInfo.td - NVPTX Register defs ---------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the PTX register file
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//===----------------------------------------------------------------------===//
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class NVPTXReg<string n> : Register<n> {
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let Namespace = "NVPTX";
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}
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class NVPTXRegClass<list<ValueType> regTypes, int alignment, dag regList>
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: RegisterClass <"NVPTX", regTypes, alignment, regList>;
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//===----------------------------------------------------------------------===//
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// Registers
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//===----------------------------------------------------------------------===//
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// Special Registers used as stack pointer
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def VRFrame : NVPTXReg<"%SP">;
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def VRFrameLocal : NVPTXReg<"%SPL">;
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// Special Registers used as the stack
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def VRDepot : NVPTXReg<"%Depot">;
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''')
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# Predicates
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outFile.write('''
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//===--- Predicate --------------------------------------------------------===//
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''')
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for i in range(0, num_regs):
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outFile.write('def P%d : NVPTXReg<"%%p%d">;\n' % (i, i))
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# Int8
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outFile.write('''
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//===--- 8-bit ------------------------------------------------------------===//
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''')
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for i in range(0, num_regs):
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outFile.write('def RC%d : NVPTXReg<"%%rc%d">;\n' % (i, i))
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# Int16
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outFile.write('''
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//===--- 16-bit -----------------------------------------------------------===//
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''')
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for i in range(0, num_regs):
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outFile.write('def RS%d : NVPTXReg<"%%rs%d">;\n' % (i, i))
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# Int32
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outFile.write('''
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//===--- 32-bit -----------------------------------------------------------===//
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''')
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for i in range(0, num_regs):
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outFile.write('def R%d : NVPTXReg<"%%r%d">;\n' % (i, i))
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# Int64
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outFile.write('''
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//===--- 64-bit -----------------------------------------------------------===//
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''')
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for i in range(0, num_regs):
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outFile.write('def RL%d : NVPTXReg<"%%rl%d">;\n' % (i, i))
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# F32
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outFile.write('''
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//===--- 32-bit float -----------------------------------------------------===//
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''')
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for i in range(0, num_regs):
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outFile.write('def F%d : NVPTXReg<"%%f%d">;\n' % (i, i))
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# F64
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outFile.write('''
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//===--- 64-bit float -----------------------------------------------------===//
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''')
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for i in range(0, num_regs):
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outFile.write('def FL%d : NVPTXReg<"%%fl%d">;\n' % (i, i))
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# Vector registers
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outFile.write('''
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//===--- Vector -----------------------------------------------------------===//
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''')
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for i in range(0, num_regs):
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outFile.write('def v2b8_%d : NVPTXReg<"%%v2b8_%d">;\n' % (i, i))
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for i in range(0, num_regs):
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outFile.write('def v2b16_%d : NVPTXReg<"%%v2b16_%d">;\n' % (i, i))
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for i in range(0, num_regs):
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outFile.write('def v2b32_%d : NVPTXReg<"%%v2b32_%d">;\n' % (i, i))
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for i in range(0, num_regs):
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outFile.write('def v2b64_%d : NVPTXReg<"%%v2b64_%d">;\n' % (i, i))
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for i in range(0, num_regs):
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outFile.write('def v4b8_%d : NVPTXReg<"%%v4b8_%d">;\n' % (i, i))
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for i in range(0, num_regs):
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outFile.write('def v4b16_%d : NVPTXReg<"%%v4b16_%d">;\n' % (i, i))
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for i in range(0, num_regs):
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outFile.write('def v4b32_%d : NVPTXReg<"%%v4b32_%d">;\n' % (i, i))
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# Argument registers
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outFile.write('''
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//===--- Arguments --------------------------------------------------------===//
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''')
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for i in range(0, num_regs):
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outFile.write('def ia%d : NVPTXReg<"%%ia%d">;\n' % (i, i))
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for i in range(0, num_regs):
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outFile.write('def la%d : NVPTXReg<"%%la%d">;\n' % (i, i))
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for i in range(0, num_regs):
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outFile.write('def fa%d : NVPTXReg<"%%fa%d">;\n' % (i, i))
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for i in range(0, num_regs):
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outFile.write('def da%d : NVPTXReg<"%%da%d">;\n' % (i, i))
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outFile.write('''
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//===----------------------------------------------------------------------===//
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// Register classes
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//===----------------------------------------------------------------------===//
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''')
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outFile.write('def Int1Regs : NVPTXRegClass<[i1], 8, (add (sequence "P%%u", 0, %d))>;\n' % (num_regs-1))
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outFile.write('def Int8Regs : NVPTXRegClass<[i8], 8, (add (sequence "RC%%u", 0, %d))>;\n' % (num_regs-1))
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outFile.write('def Int16Regs : NVPTXRegClass<[i16], 16, (add (sequence "RS%%u", 0, %d))>;\n' % (num_regs-1))
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outFile.write('def Int32Regs : NVPTXRegClass<[i32], 32, (add (sequence "R%%u", 0, %d))>;\n' % (num_regs-1))
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outFile.write('def Int64Regs : NVPTXRegClass<[i64], 64, (add (sequence "RL%%u", 0, %d))>;\n' % (num_regs-1))
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outFile.write('def Float32Regs : NVPTXRegClass<[f32], 32, (add (sequence "F%%u", 0, %d))>;\n' % (num_regs-1))
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outFile.write('def Float64Regs : NVPTXRegClass<[f64], 64, (add (sequence "FL%%u", 0, %d))>;\n' % (num_regs-1))
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outFile.write('def Int32ArgRegs : NVPTXRegClass<[i32], 32, (add (sequence "ia%%u", 0, %d))>;\n' % (num_regs-1))
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outFile.write('def Int64ArgRegs : NVPTXRegClass<[i64], 64, (add (sequence "la%%u", 0, %d))>;\n' % (num_regs-1))
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outFile.write('def Float32ArgRegs : NVPTXRegClass<[f32], 32, (add (sequence "fa%%u", 0, %d))>;\n' % (num_regs-1))
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outFile.write('def Float64ArgRegs : NVPTXRegClass<[f64], 64, (add (sequence "da%%u", 0, %d))>;\n' % (num_regs-1))
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outFile.write('''
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// Read NVPTXRegisterInfo.cpp to see how VRFrame and VRDepot are used.
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def SpecialRegs : NVPTXRegClass<[i32], 32, (add VRFrame, VRDepot)>;
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''')
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outFile.write('''
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class NVPTXVecRegClass<list<ValueType> regTypes, int alignment, dag regList,
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NVPTXRegClass sClass,
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int e,
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string n>
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: NVPTXRegClass<regTypes, alignment, regList>
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{
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NVPTXRegClass scalarClass=sClass;
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int elems=e;
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string name=n;
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}
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''')
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outFile.write('def V2F32Regs\n : NVPTXVecRegClass<[v2f32], 64, (add (sequence "v2b32_%%u", 0, %d)),\n Float32Regs, 2, ".v2.f32">;\n' % (num_regs-1))
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outFile.write('def V4F32Regs\n : NVPTXVecRegClass<[v4f32], 128, (add (sequence "v4b32_%%u", 0, %d)),\n Float32Regs, 4, ".v4.f32">;\n' % (num_regs-1))
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outFile.write('def V2I32Regs\n : NVPTXVecRegClass<[v2i32], 64, (add (sequence "v2b32_%%u", 0, %d)),\n Int32Regs, 2, ".v2.u32">;\n' % (num_regs-1))
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outFile.write('def V4I32Regs\n : NVPTXVecRegClass<[v4i32], 128, (add (sequence "v4b32_%%u", 0, %d)),\n Int32Regs, 4, ".v4.u32">;\n' % (num_regs-1))
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outFile.write('def V2F64Regs\n : NVPTXVecRegClass<[v2f64], 128, (add (sequence "v2b64_%%u", 0, %d)),\n Float64Regs, 2, ".v2.f64">;\n' % (num_regs-1))
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outFile.write('def V2I64Regs\n : NVPTXVecRegClass<[v2i64], 128, (add (sequence "v2b64_%%u", 0, %d)),\n Int64Regs, 2, ".v2.u64">;\n' % (num_regs-1))
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outFile.write('def V2I16Regs\n : NVPTXVecRegClass<[v2i16], 32, (add (sequence "v2b16_%%u", 0, %d)),\n Int16Regs, 2, ".v2.u16">;\n' % (num_regs-1))
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outFile.write('def V4I16Regs\n : NVPTXVecRegClass<[v4i16], 64, (add (sequence "v4b16_%%u", 0, %d)),\n Int16Regs, 4, ".v4.u16">;\n' % (num_regs-1))
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outFile.write('def V2I8Regs\n : NVPTXVecRegClass<[v2i8], 16, (add (sequence "v2b8_%%u", 0, %d)),\n Int8Regs, 2, ".v2.u8">;\n' % (num_regs-1))
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outFile.write('def V4I8Regs\n : NVPTXVecRegClass<[v4i8], 32, (add (sequence "v4b8_%%u", 0, %d)),\n Int8Regs, 4, ".v4.u8">;\n' % (num_regs-1))
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outFile.close()
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outFile = open('NVPTXNumRegisters.h', 'w')
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outFile.write('''
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//===-- NVPTXNumRegisters.h - PTX Register Info ---------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef NVPTX_NUM_REGISTERS_H
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#define NVPTX_NUM_REGISTERS_H
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namespace llvm {
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const unsigned NVPTXNumRegisters = %d;
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}
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#endif
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''' % num_regs)
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outFile.close()
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