Toma Tabacu 115be6213d [mips] [IAS] Add partial support for the ULHU pseudo-instruction. ... Summary: This only adds support for ULHU of an immediate address with/without a source register. It does not include support for ULHU of the address of a symbol. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9671 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240410 91177308-0d34-0410-b5e6-96231b3b80d8		2015-06-23 14:39:42 +00:00
..
AArch64	Improve the --expand-relocs handling of MachO.	2015-06-18 22:38:20 +00:00
AMDGPU
ARM	Revert r240302 ("Bring r240130 back.").	2015-06-23 11:31:32 +00:00
AsmParser
COFF
Disassembler
ELF	Revert r240302 ("Bring r240130 back.").	2015-06-23 11:31:32 +00:00
Hexagon
MachO	Revert r240302 ("Bring r240130 back.").	2015-06-23 11:31:32 +00:00
Markup
Mips	[mips] [IAS] Add partial support for the ULHU pseudo-instruction.	2015-06-23 14:39:42 +00:00
PowerPC	Properly handle the mftb instruction.	2015-06-16 16:01:15 +00:00
Sparc	Revert r240302 ("Bring r240130 back.").	2015-06-23 11:31:32 +00:00
SystemZ
X86	AVX-512: Added all forms of VPABS instruction	2015-06-23 08:19:46 +00:00