mirror of
https://github.com/c64scene-ar/llvm-6502.git
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X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
327 lines
13 KiB
TableGen
327 lines
13 KiB
TableGen
//===- X86InstrFormats.td - X86 Instruction Formats --------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// X86 Instruction Format Definitions.
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//
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// Format specifies the encoding used by the instruction. This is part of the
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// ad-hoc solution used to emit machine instruction encodings by our machine
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// code emitter.
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class Format<bits<6> val> {
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bits<6> Value = val;
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}
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def Pseudo : Format<0>; def RawFrm : Format<1>;
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def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
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def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
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def MRMSrcMem : Format<6>;
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def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
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def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
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def MRM6r : Format<22>; def MRM7r : Format<23>;
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def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
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def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
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def MRM6m : Format<30>; def MRM7m : Format<31>;
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def MRMInitReg : Format<32>;
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// ImmType - This specifies the immediate type used by an instruction. This is
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// part of the ad-hoc solution used to emit machine instruction encodings by our
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// machine code emitter.
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class ImmType<bits<3> val> {
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bits<3> Value = val;
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}
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def NoImm : ImmType<0>;
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def Imm8 : ImmType<1>;
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def Imm16 : ImmType<2>;
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def Imm32 : ImmType<3>;
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def Imm64 : ImmType<4>;
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// FPFormat - This specifies what form this FP instruction has. This is used by
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// the Floating-Point stackifier pass.
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class FPFormat<bits<3> val> {
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bits<3> Value = val;
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}
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def NotFP : FPFormat<0>;
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def ZeroArgFP : FPFormat<1>;
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def OneArgFP : FPFormat<2>;
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def OneArgFPRW : FPFormat<3>;
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def TwoArgFP : FPFormat<4>;
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def CompareFP : FPFormat<5>;
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def CondMovFP : FPFormat<6>;
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def SpecialFP : FPFormat<7>;
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// Prefix byte classes which are used to indicate to the ad-hoc machine code
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// emitter that various prefix bytes are required.
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class OpSize { bit hasOpSizePrefix = 1; }
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class AdSize { bit hasAdSizePrefix = 1; }
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class REX_W { bit hasREX_WPrefix = 1; }
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class LOCK { bit hasLockPrefix = 1; }
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class SegFS { bits<2> SegOvrBits = 1; }
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class SegGS { bits<2> SegOvrBits = 2; }
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class TB { bits<4> Prefix = 1; }
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class REP { bits<4> Prefix = 2; }
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class D8 { bits<4> Prefix = 3; }
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class D9 { bits<4> Prefix = 4; }
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class DA { bits<4> Prefix = 5; }
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class DB { bits<4> Prefix = 6; }
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class DC { bits<4> Prefix = 7; }
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class DD { bits<4> Prefix = 8; }
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class DE { bits<4> Prefix = 9; }
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class DF { bits<4> Prefix = 10; }
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class XD { bits<4> Prefix = 11; }
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class XS { bits<4> Prefix = 12; }
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class T8 { bits<4> Prefix = 13; }
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class TA { bits<4> Prefix = 14; }
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class TF { bits<4> Prefix = 15; }
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class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
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string AsmStr>
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: Instruction {
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let Namespace = "X86";
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bits<8> Opcode = opcod;
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Format Form = f;
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bits<6> FormBits = Form.Value;
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ImmType ImmT = i;
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bits<3> ImmTypeBits = ImmT.Value;
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dag OutOperandList = outs;
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dag InOperandList = ins;
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string AsmString = AsmStr;
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//
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// Attributes specific to X86 instructions...
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//
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bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
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bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
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bits<4> Prefix = 0; // Which prefix byte does this inst have?
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bit hasREX_WPrefix = 0; // Does this inst requires the REX.W prefix?
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FPFormat FPForm; // What flavor of FP instruction is this?
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bits<3> FPFormBits = 0;
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bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
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bits<2> SegOvrBits = 0; // Segment override prefix.
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}
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class I<bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern>
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: X86Inst<o, f, NoImm, outs, ins, asm> {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern>
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: X86Inst<o, f, Imm8 , outs, ins, asm> {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern>
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: X86Inst<o, f, Imm16, outs, ins, asm> {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern>
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: X86Inst<o, f, Imm32, outs, ins, asm> {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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// FPStack Instruction Templates:
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// FPI - Floating Point Instruction template.
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class FPI<bits<8> o, Format F, dag outs, dag ins, string asm>
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: I<o, F, outs, ins, asm, []> {}
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// FpI_ - Floating Point Psuedo Instruction template. Not Predicated.
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class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern>
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: X86Inst<0, Pseudo, NoImm, outs, ins, ""> {
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let FPForm = fp; let FPFormBits = FPForm.Value;
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let Pattern = pattern;
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}
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// Templates for instructions that use a 16- or 32-bit segmented address as
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// their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
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//
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// Iseg16 - 16-bit segment selector, 16-bit offset
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// Iseg32 - 16-bit segment selector, 32-bit offset
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class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern> : X86Inst<o, f, NoImm, outs, ins, asm> {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern> : X86Inst<o, f, NoImm, outs, ins, asm> {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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// SSE1 Instruction Templates:
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//
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// SSI - SSE1 instructions with XS prefix.
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// PSI - SSE1 instructions with TB prefix.
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// PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
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class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
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class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
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class PSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasSSE1]>;
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class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern>, TB, Requires<[HasSSE1]>;
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// SSE2 Instruction Templates:
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//
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// SDI - SSE2 instructions with XD prefix.
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// SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
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// SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
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// PDI - SSE2 instructions with TB and OpSize prefixes.
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// PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
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class SDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
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class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
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class SSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
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class PDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
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class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
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// SSE3 Instruction Templates:
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//
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// S3I - SSE3 instructions with TB and OpSize prefixes.
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// S3SI - SSE3 instructions with XS prefix.
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// S3DI - SSE3 instructions with XD prefix.
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class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE3]>;
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class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE3]>;
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class S3I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasSSE3]>;
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// SSSE3 Instruction Templates:
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//
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// SS38I - SSSE3 instructions with T8 prefix.
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// SS3AI - SSSE3 instructions with TA prefix.
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//
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// Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
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// uses the MMX registers. We put those instructions here because they better
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// fit into the SSSE3 instruction category rather than the MMX category.
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class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern>, T8, Requires<[HasSSSE3]>;
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class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern>, TA, Requires<[HasSSSE3]>;
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// SSE4.1 Instruction Templates:
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//
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// SS48I - SSE 4.1 instructions with T8 prefix.
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// SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
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//
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class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, T8, Requires<[HasSSE41]>;
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class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern>, TA, Requires<[HasSSE41]>;
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// SSE4.2 Instruction Templates:
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//
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// SS428I - SSE 4.2 instructions with T8 prefix.
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class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, T8, Requires<[HasSSE42]>;
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// SS42FI - SSE 4.2 instructions with TF prefix.
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class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, TF, Requires<[HasSSE42]>;
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// SS42AI = SSE 4.2 instructions with TA prefix
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class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, TA, Requires<[HasSSE42]>;
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// X86-64 Instruction templates...
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//
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class RI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, REX_W;
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class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern>, REX_W;
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class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: Ii32<o, F, outs, ins, asm, pattern>, REX_W;
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class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern>
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: X86Inst<o, f, Imm64, outs, ins, asm>, REX_W {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: SSI<o, F, outs, ins, asm, pattern>, REX_W;
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class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: SDI<o, F, outs, ins, asm, pattern>, REX_W;
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class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: PDI<o, F, outs, ins, asm, pattern>, REX_W;
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// MMX Instruction templates
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//
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// MMXI - MMX instructions with TB prefix.
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// MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
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// MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
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// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
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// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
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// MMXID - MMX instructions with XD prefix.
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// MMXIS - MMX instructions with XS prefix.
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class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
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class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX,In64BitMode]>;
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class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, TB, REX_W, Requires<[HasMMX]>;
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class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasMMX]>;
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class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
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class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasMMX]>;
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class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasMMX]>;
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