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12f33da20b
On AArch64 the pseudo instruction ldr <reg>, =... supports both 32-bit and 64-bit constants. Add support for 64 bit constants for the pools to support the pseudo instruction fully. Changes the AArch64 ldr-pseudo tests to use 32-bit registers and adds tests with 64-bit registers. Patch by Janne Grunau! Differential Revision: http://reviews.llvm.org/D4279 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213387 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
ARMAddressingModes.h | ||
ARMArchName.def | ||
ARMArchName.h | ||
ARMAsmBackend.cpp | ||
ARMBaseInfo.h | ||
ARMELFObjectWriter.cpp | ||
ARMELFStreamer.cpp | ||
ARMFixupKinds.h | ||
ARMMachObjectWriter.cpp | ||
ARMMachORelocationInfo.cpp | ||
ARMMCAsmInfo.cpp | ||
ARMMCAsmInfo.h | ||
ARMMCCodeEmitter.cpp | ||
ARMMCExpr.cpp | ||
ARMMCExpr.h | ||
ARMMCTargetDesc.cpp | ||
ARMMCTargetDesc.h | ||
ARMTargetStreamer.cpp | ||
ARMUnwindOpAsm.cpp | ||
ARMUnwindOpAsm.h | ||
ARMWinCOFFObjectWriter.cpp | ||
ARMWinCOFFStreamer.cpp | ||
CMakeLists.txt | ||
LLVMBuild.txt | ||
Makefile |