Vikram S. Adve 5cdb12f958 Minor changes. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6470 91177308-0d34-0410-b5e6-96231b3b80d8		2003-05-31 07:41:54 +00:00
..
InstrSched	Changes to allow explicit physical register arguments that have been	2003-05-31 07:37:05 +00:00
InstrSelection	Added MachineCodeForInstruction object as an argument to	2003-05-31 07:41:24 +00:00
Mapping
ModuloScheduling	so far everything compiles	2003-05-30 00:17:09 +00:00
PostOpts
PreOpts
RegAlloc	Minor changes.	2003-05-31 07:41:54 +00:00
LiveVariables.cpp	(1) Added special register class containing (for now) %fsr.	2003-05-27 00:05:23 +00:00
MachineCodeEmitter.cpp	Added saveBBreferences() for BasicBlock resolution.	2003-05-30 20:32:45 +00:00
MachineCodeForInstruction.cpp
MachineFunction.cpp
MachineInstr.cpp	Allow explicit physical registers for implicit operands.	2003-05-31 07:39:06 +00:00
MachineInstrAnnot.cpp
Makefile
PHIElimination.cpp	(1) Added special register class containing (for now) %fsr.	2003-05-27 00:05:23 +00:00
PrologEpilogInserter.cpp	(1) Added special register class containing (for now) %fsr.	2003-05-27 00:05:23 +00:00
RegAllocLocal.cpp	(1) Added special register class containing (for now) %fsr.	2003-05-27 00:05:23 +00:00
RegAllocSimple.cpp	(1) Added special register class containing (for now) %fsr.	2003-05-27 00:05:23 +00:00