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https://github.com/c64scene-ar/llvm-6502.git
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e035f65b16
Mips shift instructions DSLL, DSRL and DSRA are transformed into DSLL32, DSRL32 and DSRA32 respectively if the shift amount is between 32 and 63 Here is a description of DSLL: Purpose: Doubleword Shift Left Logical Plus 32 To execute a left-shift of a doubleword by a fixed amount--32 to 63 bits Description: GPR[rd] <- GPR[rt] << (sa+32) The 64-bit doubleword contents of GPR rt are shifted left, inserting zeros into the emptied bits; the result is placed in GPR rd. The bit-shift amount in the range 0 to 31 is specified by sa. This patch implements the direct object output of these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160277 91177308-0d34-0410-b5e6-96231b3b80d8
46 lines
957 B
LLVM
46 lines
957 B
LLVM
; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - | llvm-objdump -disassemble -triple mips64el - | FileCheck %s
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define i64 @f3(i64 %a0) nounwind readnone {
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entry:
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; CHECK: dsll ${{[0-9]+}}, ${{[0-9]+}}, 10
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%shl = shl i64 %a0, 10
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ret i64 %shl
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}
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define i64 @f4(i64 %a0) nounwind readnone {
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entry:
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; CHECK: dsra ${{[0-9]+}}, ${{[0-9]+}}, 10
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%shr = ashr i64 %a0, 10
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ret i64 %shr
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}
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define i64 @f5(i64 %a0) nounwind readnone {
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entry:
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; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 10
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%shr = lshr i64 %a0, 10
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ret i64 %shr
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}
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define i64 @f6(i64 %a0) nounwind readnone {
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entry:
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; CHECK: dsll32 ${{[0-9]+}}, ${{[0-9]+}}, 8
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%shl = shl i64 %a0, 40
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ret i64 %shl
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}
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define i64 @f7(i64 %a0) nounwind readnone {
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entry:
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; CHECK: dsra32 ${{[0-9]+}}, ${{[0-9]+}}, 8
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%shr = ashr i64 %a0, 40
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ret i64 %shr
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}
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define i64 @f8(i64 %a0) nounwind readnone {
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entry:
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; CHECK: dsrl32 ${{[0-9]+}}, ${{[0-9]+}}, 8
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%shr = lshr i64 %a0, 40
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ret i64 %shr
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}
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