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https://github.com/c64scene-ar/llvm-6502.git
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0a8fd30c1b
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12714 91177308-0d34-0410-b5e6-96231b3b80d8
394 lines
18 KiB
C++
394 lines
18 KiB
C++
//===- X86InstrSel.td - Describe the X86 Instruction Selector -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is used by the instruction selector and is used to map
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// LLVM instructions to a corresponding set of machine instructions
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//
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//
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//===----------------------------------------------------------------------===//
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include "../Target.td"
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// ret br switch invoke unwind
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// add sub mul div rem setcc (eq ne lt gt le ge)
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// and or xor sbl sbr
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// malloc free alloca load store
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// getelementptr phi cast call vanext vaarg
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class InstrSubclass<int v> {
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int Value = v;
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}
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// provide a grouping of InstrSubclasses
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class InstrSubclassCollection<string pre, string post, list<InstrSubclass> l> {
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list<InstrSubclass> List = l;
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string PreCode = pre;
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string PostCode = post;
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}
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// virtual registers
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let Namespace = "Virtual" in {
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def DestReg : Register;
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def DestRegp1 : Register; // DestReg+1
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def Op0Reg : Register;
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def Op0Regp1 : Register; // Op0Reg+1
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def Op1Reg : Register;
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def Op1Regp1 : Register; // Op1Reg+1
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def TmpReg01 : Register;
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def TmpReg01p1: Register;
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def TmpReg02 : Register;
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def TmpReg02p1: Register;
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def NullReg : Register; // represents no register
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}
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class InstrClass<string n, string fn, string pre, string post, list<InstrSubclassCollection> l> {
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string FunctionName = fn;
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string InstructionName = n;
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string PreCode = pre;
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string PostCode = post;
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// add lists of what subclasses this InstrClass supports
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list<InstrSubclassCollection> Supports = l;
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}
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// helper class to build BMI instruction
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class addedOperand<string op> {
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string Name = op;
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}
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def MBI_Reg : addedOperand<"Reg">;
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def MBI_GlobalAddr : addedOperand<"GlobalAddr">;
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def MBI_ZImm : addedOperand<"ZImm">;
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def MBI_DirectMem : addedOperand<"DirectMem">;
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def MBI_RegOffset : addedOperand<"RegOffset">;
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def MBI_FrameRef : addedOperand<"FrameRef">;
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def MBI_ConstPoolRef : addedOperand<"ConstPoolRef">;
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def MBI_CCReg : addedOperand<"CCReg">;
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def MBI_RegDef : addedOperand<"RegDef">;
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def MBI_PCDisp : addedOperand<"PCDisp">;
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def MBI_MReg : addedOperand<"MReg">;
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def MBI_SImm : addedOperand<"SImm">;
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def MBI_MBB : addedOperand<"MBB">;
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def MBI_FrameIndex : addedOperand<"FrameIndex">;
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def MBI_ConstPoolIdx : addedOperand<"ConstPoolIdx">;
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def MBI_ExternSymbol : addedOperand<"ExternSymbol">;
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class TargInstr<string n, int numops, list<addedOperand> lops> {
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string Name = n; // make this a reference to the Instruction class
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string Namespace;
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int NumOperands = numops;
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list<addedOperand> Params = lops; // will this work for mem-mem instrs, destination is implicitly a register
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} //TargInstr
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let Namespace = "Virtual" in {
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// virtual instructions for creating registers
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def CreateRegInt : TargInstr<"CreateRegInt",0,[]>;
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def CreateRegByte : TargInstr<"CreateRegByte",0,[]>;
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def CreateRegShort: TargInstr<"CreateRegShort",0,[]>;
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def CreateRegLong : TargInstr<"CreateRegLong",0,[]>;
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def CreateRegUInt : TargInstr<"CreateRegUInt",0,[]>;
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def CreateRegUByte : TargInstr<"CreateRegUByte",0,[]>;
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def CreateRegUShort: TargInstr<"CreateRegUShort",0,[]>;
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def CreateRegULong : TargInstr<"CreateRegULong",0,[]>;
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def CreateRegFloat : TargInstr<"CreateRegFloat",0,[]>;
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def CreateRegDouble : TargInstr<"CreateRegDouble",0,[]>;
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def CreateRegPointer: TargInstr<"CreateRegPointer",0,[]>;
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def NullInstr : TargInstr<"NullInstruction",0,[]>; // ignored
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}
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class TargInstrSet<InstrClass c, string pre, string post, list<InstrSubclass> l, list<TargInstr> targs, list<list<string>> r> {
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InstrClass Class = c;
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list<InstrSubclass> List = l;
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list<TargInstr> Instructions = targs;
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list< list<string> > Operands = r; // generalized for all operand types
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string PreCode = pre;
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string PostCode = post;
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}
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// --------------------------------------------------------------------
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// Begin architecture-specific information
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// --------------------------------------------------------------------
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include "X86RegisterInfo.td"
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include "X86InstrSelInfo.td"
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// set up the subclasses of instructions
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// value is what the subclass's case value
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def cByte : InstrSubclass<1>;
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def cInt : InstrSubclass<2>;
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def cShort : InstrSubclass<3>;
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def cFP : InstrSubclass<4>;
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def cLong : InstrSubclass<5>;
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def EQ : InstrSubclass<1>;
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def NE : InstrSubclass<2>;
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def LT : InstrSubclass<3>;
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def GE : InstrSubclass<4>;
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def GT : InstrSubclass<5>;
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def LE : InstrSubclass<6>;
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def True : InstrSubclass<1>;
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def False : InstrSubclass<0>;
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def NegOne : InstrSubclass<-1>;
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def PosOne : InstrSubclass<1>;
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def Cons :InstrSubclass<2>;
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def Other : InstrSubclass<0>;
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def Regular: InstrSubclass<0>;
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def Zero : InstrSubclass<0>;
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def NoOps : InstrSubclass<0>;
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def Ops : InstrSubclass<1>;
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def Signed : InstrSubclass<0>;
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def Unsigned : InstrSubclass<1>;
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def SuccessorIsNextBB : InstrSubclass<0>;
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def SuccessorIsNotNextBB: InstrSubclass<1>;
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def Cond: InstrSubclass<0>;
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def Uncond: InstrSubclass<1>;
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def ConstTwo: InstrSubclass<2>;
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def ConstNotTwo: InstrSubclass<3>;
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def Reg: InstrSubclass<6>;
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// group subclasses, specify how to determine instruction subclass
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def OperandSize: InstrSubclassCollection<"unsigned OperandSize = getClassB(Op0Val->getType());","", [cByte, cShort, cInt, cFP, cLong]>;
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def Conditional: InstrSubclassCollection<"unsigned Conditional;", "", [EQ, NE, LT, GE, GT, LE]>;
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def SpecialCase: InstrSubclassCollection<"unsigned SpecialCase;", "", [True, False]>;
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//TODO write funcs for separating out special cases
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def AddSpecialCases: InstrSubclassCollection<"Subclasses AddSpecialCases = Other;", "", [NegOne,PosOne,Cons,Other]>;
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def SubSpecialCases: InstrSubclassCollection<"unsigned SubSpecialCases = Other;", "", [NegOne,PosOne,Cons,Other]>;
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def XorSpecialCases: InstrSubclassCollection<"unsigned XorSpecialCases = Other;","", [NegOne,Other]>;
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// Instruction subclasses, as defined in llvm/Instructions.h:
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// iTerminators.h : ReturnInst, BranchInst, SwitchInst, InvokeInst, UnwindInst
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// iPHINode.h : PHINode,
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// iOperators.h : SetCondInst,
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// iMemory.h : AllocationInst, MallocInst, AllocaInst, FreeInst, LoadInst, StoreInst, GetElementPtrInst,
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// iOther.h : CastInst, CallInst, ShiftInst, VANextInst, VAArgInst,
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// InstrTypes.h : TerminatorInst, BinaryOperator
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// general classes of LLVM instructions, and the subclass sets that apply to them
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def add : InstrClass<"BinaryOperator","Add","","",[AddSpecialCases, OperandSize]>;
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def sub : InstrClass<"BinaryOperator","Sub","","",[SubSpecialCases, OperandSize]>;
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// def mul : InstrClass<"BinaryOperator","Mul","","",[OperandSize]>;
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// def div : InstrClass<"BinaryOperator","Div","","",[OperandSize]>;
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// def rem : InstrClass<"BinaryOperator","Rem","","",[OperandSize]>;
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def logic_and : InstrClass<"BinaryOperator","And","","",[OperandSize]>;
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def logic_or : InstrClass<"BinaryOperator","Or","","",[OperandSize]>;
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def logic_xor : InstrClass<"BinaryOperator","Xor","","",[XorSpecialCases, OperandSize]>;
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// //def mov : InstrClass<"ShiftInst","Mov","","",[OperandSize]>;
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// def setcc: InstrClass<"SetCondInst","SetCondInst","","",[OperandSize]>;
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// def branch : InstrClass<"BranchInst","BranchInst","","",[Conditional]>;
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// def retrn : InstrClass<"ReturnInst","ReturnInst","","",[]>;
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// definition of machine instructions for instruction subclasses
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// ADD
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def ADD_Other_cByte : TargInstrSet<add,"","",[Other,cByte],[CreateRegByte,ADDrr8],[["EAX"],["EAX","Op0Reg","Op1Reg"]]>;
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def ADD_Other_cShort : TargInstrSet<add,"","",[Other,cShort],[ADDrr16],[["DestReg","Op0Reg","Op1Reg"]]>;
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def ADD_Other_cInt : TargInstrSet<add,"","",[Other,cInt],[ADDrr32],[["DestReg","Op0Reg","Op1Reg"]]>;
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def ADD_Other_cLong : TargInstrSet<add,"","",[Other,cLong],[ADDrr32,ADCrr32],[["DestReg","Op0Reg","Op1Reg"],["DestReg","Op0Reg","Op1Reg"]]>;
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def ADD_Other_cFP : TargInstrSet<add,"","",[Other,cFP],[FpADD],[["DestReg","Op0Reg","Op1Reg"]]>;
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def ADD_Constant_cByte : TargInstrSet<add,"","",[Cons,cByte],[ADDri8],[["DestReg","Op0Reg","Op1Reg"]]>;
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def ADD_Constant_cShort :TargInstrSet<add,"","",[Cons,cShort],[ADDri16],[["DestReg","Op0Reg","Op1Reg"]]>;
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def ADD_Constant_cInt :TargInstrSet<add,"","",[Cons,cInt],[ADDri32],[["DestReg","Op0Reg","Op1Reg"]]>;
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def ADD_PosOne_cByte : TargInstrSet<add,"","",[PosOne,cByte],[INCr8],[["DestReg","Op0Reg"]]>;
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def ADD_PosOne_cShort : TargInstrSet<add,"","",[PosOne,cShort],[INCr16],[["DestReg","Op0Reg"]]>;
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def ADD_PosOne_cInt : TargInstrSet<add,"","",[PosOne,cInt],[INCr32],[["DestReg","Op0Reg"]]>;
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def ADD_NegOne_cByte : TargInstrSet<add,"","",[NegOne,cByte],[DECr8],[["DestReg","Op0Reg"]]>;
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def ADD_NegOne_cShort : TargInstrSet<add,"","",[NegOne,cShort],[DECr16],[["DestReg","Op0Reg"]]>;
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def ADD_NegOne_cInt : TargInstrSet<add,"","",[NegOne,cInt],[DECr32],[["DestReg","Op0Reg"]]>;
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// SUBTRACT
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def SUB_Other_cByte : TargInstrSet<sub,"","",[Other,cByte],[CreateRegByte,SUBrr8],[["EAX"],["EAX","Op0Reg","Op1Reg"]]>;
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def SUB_Other_cShort : TargInstrSet<sub,"","",[Other,cShort],[SUBrr16],[["DestReg","Op0Reg","Op1Reg"]]>;
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def SUB_Other_cInt : TargInstrSet<sub,"","",[Other,cInt],[SUBrr32],[["DestReg","Op0Reg","Op1Reg"]]>;
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def SUB_Other_cLong : TargInstrSet<sub,"","",[Other,cLong],[SUBrr32,SUBrr32],[["DestReg","Op0Reg","Op1Reg"],["DestReg","Op0Reg","Op1Reg"]]>;
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def SUB_Other_cFP : TargInstrSet<sub,"","",[Other,cFP],[FpSUB],[["DestReg","Op0Reg","Op1Reg"]]>;
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def SUB_Constant_cByte : TargInstrSet<sub,"","",[Cons,cByte],[SUBri8],[["DestReg","Op0Reg","Op1Reg"]]>;
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def SUB_Constant_cShort :TargInstrSet<sub,"","",[Cons,cShort],[SUBri16],[["DestReg","Op0Reg","Op1Reg"]]>;
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def SUB_Constant_cInt :TargInstrSet<sub,"","",[Cons,cInt],[SUBri32],[["DestReg","Op0Reg","Op1Reg"]]>;
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def SUB_PosOne_cByte : TargInstrSet<sub,"","",[PosOne,cByte],[DECr8],[["DestReg","Op0Reg"]]>;
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def SUB_PosOne_cShort : TargInstrSet<sub,"","",[PosOne,cShort],[DECr16],[["DestReg","Op0Reg"]]>;
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def SUB_PosOne_cInt : TargInstrSet<sub,"","",[PosOne,cInt],[DECr32],[["DestReg","Op0Reg"]]>;
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def SUB_NegOne_cByte : TargInstrSet<sub,"","",[NegOne,cByte],[INCr8],[["DestReg","Op0Reg"]]>;
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def SUB_NegOne_cShort : TargInstrSet<sub,"","",[NegOne,cShort],[INCr16],[["DestReg","Op0Reg"]]>;
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def SUB_NegOne_cInt : TargInstrSet<sub,"","",[NegOne,cInt],[INCr32],[["DestReg","Op0Reg"]]>;
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// def SHIFT_S_L_Const_Byte :
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// def SHIFT_S_L_Const_Short :
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// def SHIFT_S_L_Const_Int :
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// def SHIFT_S_L_Const_SHLDIR32 :
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// def SHIFT_S_L_Reg_Byte :
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// def SHIFT_S_L_Reg_Short :
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// def SHIFT_S_L_Reg_Int :
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// def SHIFT_S_R_Const_Byte :
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// def SHIFT_S_R_Const_Short :
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// def SHIFT_S_R_Const_Int :
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// def SHIFT_S_R_Const_SHRDIR32 :
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// def SHIFT_S_R_Reg_Byte :
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// def SHIFT_S_R_Reg_Short :
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// def SHIFT_S_R_Reg_Int :
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// def SHIFT_U_L_Const_Byte :
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// def SHIFT_U_L_Const_Short :
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// def SHIFT_U_L_Const_Int :
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// def SHIFT_U_L_Const_SHLDIR32 :
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// def SHIFT_U_L_Reg_Byte :
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// def SHIFT_U_L_Reg_Short :
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// def SHIFT_U_L_Reg_Int :
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// def SHIFT_U_R_Const_Byte :
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// def SHIFT_U_R_Const_Short :
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// def SHIFT_U_R_Const_Int :
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// def SHIFT_U_R_Const_SHRDIR32 :
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// def SHIFT_U_R_Reg_Byte :
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// def SHIFT_U_R_Reg_Short :
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// def SHIFT_U_R_Reg_Int :
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// def CMP_i_Byte : TargInstrSet<setcc,"","",[Constant,cByte],[CMPri8],[["DestReg","Op0Reg","Op1Val"]]>;
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// def CMP_i_Short : TargInstrSet<setcc,"","",[Constant,cShort],[CMPri16],[["DestReg","Op0Reg","Op1Val"]]>;
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// def CMP_i_Int : TargInstrSet<setcc,"","",[Constant,cInt],[CMPri32],[["DestReg","Op0Reg","Op1Val"]]>;
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// //def CMP_i_Long : // not supported
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// def CMP_z_Byte : TargInstrSet<setcc,"ConstantInt *CI = dyn_cast<ConstantInt>(Op1); uint64_t Op1v = cast<ConstantInt>(CI)->getRawValue(); Op1v &= (1ULL << (8 << Class)) - 1;","",[Zero,cByte],[TESTrr8],[["DestReg","Op0Reg","Op0Reg"]]>;
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// def CMP_z_Short : TargInstrSet<setcc,"ConstantInt *CI = dyn_cast<ConstantInt>(Op1); uint64_t Op1v = cast<ConstantInt>(CI)->getRawValue(); Op1v &= (1ULL << (8 << Class)) - 1;","",[Zero,cShort],[TESTrr16],[["DestReg","Op0Reg","Op0Reg"]]>;
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// def CMP_z_Int : TargInstrSet<setcc,"ConstantInt *CI = dyn_cast<ConstantInt>(Op1); uint64_t Op1v = cast<ConstantInt>(CI)->getRawValue(); Op1v &= (1ULL << (8 << Class)) - 1;","",[Zero,cInt],[TESTrr32],[["DestReg","Op0Reg","Op0Reg"]]>;
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// //def CMP_z_Long : // not supported
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// def CMP_r_Byte : TargInstrSet<setcc,"","",[Regular,cByte],[CMPrr8],[["NullReg","Op0Reg","Op1Reg"]]>;
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// def CMP_r_Short : TargInstrSet<setcc,"","",[Regular,cShort],[CMPrr16],[["NullReg","Op0Reg","Op1Reg"]]>;
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// def CMP_r_Int : TargInstrSet<setcc,"","",[Regular,cInt],[CMPrr32],[["NullReg","Op0Reg","Op1Reg"]]>;
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// //def CMP_r_Long : // two cases of long, depending on num of operands
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// def CMP_r_FP : TargInstrSet<setcc,"","",[Regular,cFP],[FpUCOM,FNSTSWr8,SAHF],[["NullReg","Op0Reg","Op1Reg"],["NullReg"],["NullReg"]]>;
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// def RET_NoOps : TargInstrSet<retrn,"","",[NoOps],[FP_REG_KILL,RET],[["NullReg"],["NullReg"]]>;
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// def RET_Op_Byte : TargInstrSet<retrn,"promote32(X86::EAX, ValueRecord(Op0Reg, Op0Val->getType()));","",[Ops,cByte],[IMPLICIT_USE],[["NullReg","EAX","ESP"]]>;
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// def RET_Op_Short : TargInstrSet<retrn,"promote32(X86::EAX, ValueRecord(Op0Reg, Op0Val->getType()));","",[Ops,cShort],[IMPLICIT_USE],[["NullReg","EAX","ESP"]]>;
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// def RET_Op_Int : TargInstrSet<retrn,"promote32(X86::EAX, ValueRecord(Op0Reg, Op0Val->getType()));","",[Ops,cInt],[IMPLICIT_USE],[["NullReg","EAX","ESP"]]>;
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// def RET_Op_FP : TargInstrSet<retrn,"","",[Ops,cFP],[FpSETRESULT,IMPLICIT_USE],[["NullReg","Op0Reg"],["NullReg","STO","ESP"]]>;
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// def RET_Op_Long : TargInstrSet<retrn,"","",[Ops,cLong],[MOVrr32,MOVrr32,IMPLICIT_USE],[["EAX","Op0Reg"],["EDX","Op0Reg+1"],["NullReg","EAX","EDX","ESP"]]>;
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// def BR_Uncond : TargInstrSet<branch,"","",[Uncond],[FP_REG_KILL,JMP],[["NullReg"],["NullReg","I.getSuccessor(0);"]]>;
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// def BR_Cond_S_EQ :
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// def BR_Cond_S_NE
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// def BR_Cond_S_B
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// def BR_Cond_S_AE
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// def BR_Cond_S_A
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// def BR_Cond_S_BE
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// def BR_Cond_U_EQ
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// def BR_Cond_U_NE
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// def BR_Cond_U_LT
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// def BR_Cond_U_GE
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// def BR_Cond_U_GT
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// def BR_Cond_U_LE
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// def BR_Cond_U_S
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// def BR_Cond_U_NS
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// def CALL_Byte
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// def CALL_Short
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// def CALL_Int
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// def CALL_Long
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// def CALL_FP
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def AND_Byte : TargInstrSet<logic_and,"","",[cByte],[ANDrr8],[["DestReg","Op0Reg","Op1Reg"]]>;
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def AND_Short : TargInstrSet<logic_and,"","",[cShort],[ANDrr16],[["DestReg","Op0Reg","Op1Reg"]]>;
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def AND_Int : TargInstrSet<logic_and,"","",[cInt],[ANDrr32],[["DestReg","Op0Reg","Op1Reg"]]>;
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def AND_Long : TargInstrSet<logic_and,"","",[cLong],[ANDrr32,ANDrr32],[["DestReg","Op0Reg","Op1Reg"],["DestReg+1","Op0Reg+1","Op1Reg+1"]]>;
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def OR_Byte : TargInstrSet<logic_or,"","",[cByte],[ORrr8],[["DestReg","Op0Reg","Op1Reg"]]>;
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def OR_Short : TargInstrSet<logic_or,"","",[cShort],[ORrr16],[["DestReg","Op0Reg","Op1Reg"]]>;
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def OR_Int : TargInstrSet<logic_or,"","",[cInt],[ORrr32],[["DestReg","Op0Reg","Op1Reg"]]>;
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def OR_Long : TargInstrSet<logic_or,"","",[cLong],[ORrr32,ORrr32],[["DestReg","Op0Reg","Op1Reg"],["DestReg+1","Op0Reg+1","Op1Reg+1"]]>;
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def XOR_NegOne_Byte : TargInstrSet<logic_xor,"","",[NegOne,cByte],[NOTr8],[["DestReg","Op0Reg"]]>;
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def XOR_NegOne_Short: TargInstrSet<logic_xor,"","",[NegOne,cShort],[NOTr16],[["DestReg","Op0Reg"]]>;
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def XOR_NegOne_Int : TargInstrSet<logic_xor,"","",[NegOne,cInt],[NOTr32],[["DestReg","Op0Reg"]]>;
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//def XOR_NegOne_Long : // not supported (treat as regular long XOR)
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def XOR_Other_Byte : TargInstrSet<logic_xor,"","",[Other,cByte],[XORrr8],[["DestReg","Op0Reg","Op1Reg"]]>;
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def XOR_Other_Short : TargInstrSet<logic_xor,"","",[Other,cByte],[XORrr16],[["DestReg","Op0Reg","Op1Reg"]]>;
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def XOR_Other_Int : TargInstrSet<logic_xor,"","",[Other,cByte],[XORrr32],[["DestReg","Op0Reg","Op1Reg"]]>;
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def XOR_Other_Long : TargInstrSet<logic_xor,"","",[Other,cLong],[XORrr32,XORrr32],[["DestReg","Op0Reg","Op1Reg"],["DestReg+1","Op0Reg+1","Op1Reg+1"]]>;
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// // TODO support for arbitrary values as operand arguments
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// // or make ConstantInt versions as well-known variables
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// // ConstantInt, unsigned Val
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// def MUL_ConstTwo_Byte : TargInstrSet<mul,"ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1)); unsigned Val = (unsigned)CI->getRawValue(); unsigned Shift = ExactLog2(Val);","",[ConstTwo,cByte],[SHLir32],[["DestReg","Op0Reg","Shift-1"]]>;
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// def MUL_ConstTwo_Short : TargInstrSet<mul,"ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1)); unsigned Val = (unsigned)CI->getRawValue(); unsigned Shift = ExactLog2(Val);","",[ConstTwo,cShort],[SHLir32],[["DestReg","Op0Reg","Shift-1"]]>;
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// def MUL_ConstTwo_Int : TargInstrSet<mul,"ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1)); unsigned Val = (unsigned)CI->getRawValue(); unsigned Shift = ExactLog2(Val);","",[ConstTwo,cInt],[SHLir32],[["DestReg","Op0Reg","Shift-1"]]>;
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// def MUL_ConstNotTwo_Byte : TargInstrSet<mul,"","",[ConstNotTwo,cByte],[CreateRegByte,MOVir8,MOVrr8,MULr8,MOVrr8],[["tmpReg"],["tmpReg","ConstRHS"],["AL","Op0Reg"],["NullReg","Op1Reg"],["DestReg","AL"]]>; //TODO fixme, define ConstRHS
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// def MUL_ConstNotTwo_Short : TargInstrSet<mul,"","",[ConstNotTwo,cShort],[IMULri16],[["DestReg","Op0Reg","Val"]]>;
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// def MUL_ConstNotTwo_Int : TargInstrSet<mul,"","",[ConstNotTwo,cInt],[IMULri32],[["DestReg","Op0Reg","Val"]]>;
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// //def MUL_ConstNotTwo_Long :
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// //def MUL_ConstNotTwo_FP :
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// def MUL_Reg_Byte : TargInstrSet<mul,"","",[Reg,cByte],[MOVrr8,MULr8,MOVrr8],[["AL","Op0Reg"],["NullReg","Op1Reg"],["DestReg","AL"]]>;
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// def MUL_Reg_Short : TargInstrSet<mul,"","",[Reg,cShort],[IMULrr16],[["DestReg","Op0Reg","Op1Reg"]]>;
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// def MUL_Reg_Int : TargInstrSet<mul,"","",[Reg,cInt],[IMULrr32],[["DestReg","Op0Reg","Op1Reg"]]>;
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// //def MUL_Reg_Long : // not supported (assert)
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// def MUL_Reg_FP : TargInstrSet<mul,"","",[Reg,cFP],[FpMUL],[["DestReg","Op0Reg","Op1Reg"]]>;
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// def STO_Byte
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// def STO_Short
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// def STO_Int
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// def STO_FP
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// def STO_Long
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// DIVREM
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// CAST
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// PHI
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// LOAD ARGS TO VIRTUAL REGS
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// COPY CONSTANT
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//TODO
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// handling various operand options
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// allowing for arbitrary code or operand arguments
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// generate skeletons for selector function
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//
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