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GCC accepts 'cc' as an alias for 'cr0', and we need to do the same when processing inline asm constraints. This had previously been implemented using a non-allocatable register, named 'cc', that was listed as an alias of 'cr0', but the infrastructure does not seem to support this properly (neither the register allocator nor the scheduler properly accounts for the alias). Instead, we can just process this as a naming alias inside of the inline asm constraint-processing code, so we'll do that instead. There are two regression tests, one where the post-RA scheduler did the wrong thing with the non-allocatable alias, and one where the register allocator did the wrong thing. Fixes PR21742. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223708 91177308-0d34-0410-b5e6-96231b3b80d8
304 lines
11 KiB
TableGen
304 lines
11 KiB
TableGen
//===-- PPCRegisterInfo.td - The PowerPC Register File -----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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let Namespace = "PPC" in {
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def sub_lt : SubRegIndex<1>;
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def sub_gt : SubRegIndex<1, 1>;
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def sub_eq : SubRegIndex<1, 2>;
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def sub_un : SubRegIndex<1, 3>;
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def sub_32 : SubRegIndex<32>;
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def sub_64 : SubRegIndex<64>;
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def sub_128 : SubRegIndex<128>;
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}
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class PPCReg<string n> : Register<n> {
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let Namespace = "PPC";
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}
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// We identify all our registers with a 5-bit ID, for consistency's sake.
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// GPR - One of the 32 32-bit general-purpose registers
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class GPR<bits<5> num, string n> : PPCReg<n> {
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let HWEncoding{4-0} = num;
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}
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// GP8 - One of the 32 64-bit general-purpose registers
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class GP8<GPR SubReg, string n> : PPCReg<n> {
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let HWEncoding = SubReg.HWEncoding;
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let SubRegs = [SubReg];
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let SubRegIndices = [sub_32];
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}
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// SPR - One of the 32-bit special-purpose registers
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class SPR<bits<10> num, string n> : PPCReg<n> {
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let HWEncoding{9-0} = num;
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}
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// FPR - One of the 32 64-bit floating-point registers
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class FPR<bits<5> num, string n> : PPCReg<n> {
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let HWEncoding{4-0} = num;
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}
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// VF - One of the 32 64-bit floating-point subregisters of the vector
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// registers (used by VSX).
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class VF<bits<5> num, string n> : PPCReg<n> {
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let HWEncoding{4-0} = num;
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let HWEncoding{5} = 1;
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}
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// VR - One of the 32 128-bit vector registers
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class VR<VF SubReg, string n> : PPCReg<n> {
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let HWEncoding{4-0} = SubReg.HWEncoding{4-0};
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let HWEncoding{5} = 0;
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let SubRegs = [SubReg];
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let SubRegIndices = [sub_64];
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}
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// VSRL - One of the 32 128-bit VSX registers that overlap with the scalar
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// floating-point registers.
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class VSRL<FPR SubReg, string n> : PPCReg<n> {
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let HWEncoding = SubReg.HWEncoding;
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let SubRegs = [SubReg];
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let SubRegIndices = [sub_64];
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}
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// VSRH - One of the 32 128-bit VSX registers that overlap with the vector
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// registers.
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class VSRH<VR SubReg, string n> : PPCReg<n> {
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let HWEncoding{4-0} = SubReg.HWEncoding{4-0};
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let HWEncoding{5} = 1;
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let SubRegs = [SubReg];
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let SubRegIndices = [sub_128];
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}
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// CR - One of the 8 4-bit condition registers
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class CR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
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let HWEncoding{2-0} = num;
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let SubRegs = subregs;
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}
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// CRBIT - One of the 32 1-bit condition register fields
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class CRBIT<bits<5> num, string n> : PPCReg<n> {
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let HWEncoding{4-0} = num;
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}
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// General-purpose registers
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foreach Index = 0-31 in {
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def R#Index : GPR<Index, "r"#Index>, DwarfRegNum<[-2, Index]>;
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}
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// 64-bit General-purpose registers
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foreach Index = 0-31 in {
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def X#Index : GP8<!cast<GPR>("R"#Index), "r"#Index>,
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DwarfRegNum<[Index, -2]>;
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}
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// Floating-point registers
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foreach Index = 0-31 in {
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def F#Index : FPR<Index, "f"#Index>,
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DwarfRegNum<[!add(Index, 32), !add(Index, 32)]>;
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}
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// Floating-point vector subregisters (for VSX)
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foreach Index = 0-31 in {
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def VF#Index : VF<Index, "vs" # !add(Index, 32)>;
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}
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// Vector registers
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foreach Index = 0-31 in {
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def V#Index : VR<!cast<VF>("VF"#Index), "v"#Index>,
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DwarfRegNum<[!add(Index, 77), !add(Index, 77)]>;
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}
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// VSX registers
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foreach Index = 0-31 in {
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def VSL#Index : VSRL<!cast<FPR>("F"#Index), "vs"#Index>,
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DwarfRegAlias<!cast<FPR>("F"#Index)>;
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}
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foreach Index = 0-31 in {
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def VSH#Index : VSRH<!cast<VR>("V"#Index), "vs" # !add(Index, 32)>,
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DwarfRegAlias<!cast<VR>("V"#Index)>;
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}
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// The reprsentation of r0 when treated as the constant 0.
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def ZERO : GPR<0, "0">;
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def ZERO8 : GP8<ZERO, "0">;
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// Representations of the frame pointer used by ISD::FRAMEADDR.
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def FP : GPR<0 /* arbitrary */, "**FRAME POINTER**">;
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def FP8 : GP8<FP, "**FRAME POINTER**">;
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// Representations of the base pointer used by setjmp.
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def BP : GPR<0 /* arbitrary */, "**BASE POINTER**">;
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def BP8 : GP8<BP, "**BASE POINTER**">;
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// Condition register bits
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def CR0LT : CRBIT< 0, "0">;
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def CR0GT : CRBIT< 1, "1">;
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def CR0EQ : CRBIT< 2, "2">;
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def CR0UN : CRBIT< 3, "3">;
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def CR1LT : CRBIT< 4, "4">;
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def CR1GT : CRBIT< 5, "5">;
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def CR1EQ : CRBIT< 6, "6">;
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def CR1UN : CRBIT< 7, "7">;
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def CR2LT : CRBIT< 8, "8">;
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def CR2GT : CRBIT< 9, "9">;
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def CR2EQ : CRBIT<10, "10">;
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def CR2UN : CRBIT<11, "11">;
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def CR3LT : CRBIT<12, "12">;
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def CR3GT : CRBIT<13, "13">;
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def CR3EQ : CRBIT<14, "14">;
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def CR3UN : CRBIT<15, "15">;
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def CR4LT : CRBIT<16, "16">;
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def CR4GT : CRBIT<17, "17">;
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def CR4EQ : CRBIT<18, "18">;
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def CR4UN : CRBIT<19, "19">;
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def CR5LT : CRBIT<20, "20">;
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def CR5GT : CRBIT<21, "21">;
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def CR5EQ : CRBIT<22, "22">;
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def CR5UN : CRBIT<23, "23">;
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def CR6LT : CRBIT<24, "24">;
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def CR6GT : CRBIT<25, "25">;
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def CR6EQ : CRBIT<26, "26">;
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def CR6UN : CRBIT<27, "27">;
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def CR7LT : CRBIT<28, "28">;
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def CR7GT : CRBIT<29, "29">;
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def CR7EQ : CRBIT<30, "30">;
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def CR7UN : CRBIT<31, "31">;
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// Condition registers
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let SubRegIndices = [sub_lt, sub_gt, sub_eq, sub_un] in {
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def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68, 68]>;
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def CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69, 69]>;
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def CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70, 70]>;
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def CR3 : CR<3, "cr3", [CR3LT, CR3GT, CR3EQ, CR3UN]>, DwarfRegNum<[71, 71]>;
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def CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72, 72]>;
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def CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73, 73]>;
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def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74, 74]>;
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def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>;
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}
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// Link register
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def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
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//let Aliases = [LR] in
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def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
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// Count register
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def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
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def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
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// VRsave register
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def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
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// Carry bit. In the architecture this is really bit 0 of the XER register
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// (which really is SPR register 1); this is the only bit interesting to a
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// compiler.
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def CARRY: SPR<1, "ca">;
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// FP rounding mode: bits 30 and 31 of the FP status and control register
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// This is not allocated as a normal register; it appears only in
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// Uses and Defs. The ABI says it needs to be preserved by a function,
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// but this is not achieved by saving and restoring it as with
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// most registers, it has to be done in code; to make this work all the
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// return and call instructions are described as Uses of RM, so instructions
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// that do nothing but change RM will not get deleted.
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// Also, in the architecture it is not really a SPR; 512 is arbitrary.
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def RM: SPR<512, "**ROUNDING MODE**">;
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/// Register classes
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// Allocate volatiles first
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// then nonvolatiles in reverse order since stmw/lmw save from rN to r31
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def GPRC : RegisterClass<"PPC", [i32], 32, (add (sequence "R%u", 2, 12),
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(sequence "R%u", 30, 13),
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R31, R0, R1, FP, BP)>;
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def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12),
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(sequence "X%u", 30, 14),
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X31, X13, X0, X1, FP8, BP8)>;
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// For some instructions r0 is special (representing the value 0 instead of
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// the value in the r0 register), and we use these register subclasses to
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// prevent r0 from being allocated for use by those instructions.
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def GPRC_NOR0 : RegisterClass<"PPC", [i32], 32, (add (sub GPRC, R0), ZERO)>;
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def G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO8)>;
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// Allocate volatiles first, then non-volatiles in reverse order. With the SVR4
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// ABI the size of the Floating-point register save area is determined by the
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// allocated non-volatile register with the lowest register number, as FP
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// register N is spilled to offset 8 * (32 - N) below the back chain word of the
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// previous stack frame. By allocating non-volatiles in reverse order we make
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// sure that the Floating-point register save area is always as small as
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// possible because there aren't any unused spill slots.
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def F8RC : RegisterClass<"PPC", [f64], 64, (add (sequence "F%u", 0, 13),
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(sequence "F%u", 31, 14))>;
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def F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>;
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def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128,
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(add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11,
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V12, V13, V14, V15, V16, V17, V18, V19, V31, V30,
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V29, V28, V27, V26, V25, V24, V23, V22, V21, V20)>;
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// VSX register classes (the allocation order mirrors that of the corresponding
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// subregister classes).
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def VSLRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
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(add (sequence "VSL%u", 0, 13),
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(sequence "VSL%u", 31, 14))>;
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def VSHRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
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(add VSH2, VSH3, VSH4, VSH5, VSH0, VSH1, VSH6, VSH7,
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VSH8, VSH9, VSH10, VSH11, VSH12, VSH13, VSH14,
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VSH15, VSH16, VSH17, VSH18, VSH19, VSH31, VSH30,
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VSH29, VSH28, VSH27, VSH26, VSH25, VSH24, VSH23,
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VSH22, VSH21, VSH20)>;
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def VSRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
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(add VSLRC, VSHRC)>;
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// Register classes for the 64-bit "scalar" VSX subregisters.
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def VFRC : RegisterClass<"PPC", [f64], 64,
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(add VF2, VF3, VF4, VF5, VF0, VF1, VF6, VF7,
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VF8, VF9, VF10, VF11, VF12, VF13, VF14,
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VF15, VF16, VF17, VF18, VF19, VF31, VF30,
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VF29, VF28, VF27, VF26, VF25, VF24, VF23,
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VF22, VF21, VF20)>;
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def VSFRC : RegisterClass<"PPC", [f64], 64, (add F8RC, VFRC)>;
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def CRBITRC : RegisterClass<"PPC", [i1], 32,
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(add CR2LT, CR2GT, CR2EQ, CR2UN,
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CR3LT, CR3GT, CR3EQ, CR3UN,
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CR4LT, CR4GT, CR4EQ, CR4UN,
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CR5LT, CR5GT, CR5EQ, CR5UN,
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CR6LT, CR6GT, CR6EQ, CR6UN,
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CR7LT, CR7GT, CR7EQ, CR7UN,
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CR1LT, CR1GT, CR1EQ, CR1UN,
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CR0LT, CR0GT, CR0EQ, CR0UN)> {
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let Size = 32;
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}
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def CRRC : RegisterClass<"PPC", [i32], 32, (add CR0, CR1, CR5, CR6,
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CR7, CR2, CR3, CR4)>;
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// The CTR registers are not allocatable because they're used by the
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// decrement-and-branch instructions, and thus need to stay live across
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// multiple basic blocks.
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def CTRRC : RegisterClass<"PPC", [i32], 32, (add CTR)> {
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let isAllocatable = 0;
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}
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def CTRRC8 : RegisterClass<"PPC", [i64], 64, (add CTR8)> {
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let isAllocatable = 0;
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}
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def VRSAVERC : RegisterClass<"PPC", [i32], 32, (add VRSAVE)>;
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def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY)> {
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let CopyCost = -1;
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}
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