llvm-6502/test/CodeGen
Hal Finkel 3ab10c1918 [PowerPC] Remove zexts after i32 ctlz
The 64-bit semantics of cntlzw are not special, the 32-bit population count is
stored as a 64-bit value in the range [0,32]. As a result, it is always zero
extended, and it can be added to the PPCISelDAGToDAG peephole optimization as a
frontier instruction for the removal of unnecessary zero extensions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225192 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-05 18:52:29 +00:00
..
AArch64 [AArch64] Improve codegen of store lane instructions by avoiding GPR usage. 2015-01-05 17:10:26 +00:00
ARM Emit the build attribute Tag_conformance. 2015-01-05 13:12:17 +00:00
CPP
Generic
Hexagon [Hexagon] Adding reg-reg indexed load forms. 2014-12-30 18:58:47 +00:00
Inputs
Mips
MSP430
NVPTX
PowerPC [PowerPC] Remove zexts after i32 ctlz 2015-01-05 18:52:29 +00:00
R600
SPARC
SystemZ
Thumb
Thumb2
X86 [X86][SSE] Added vector packing test for pr12412 2015-01-04 19:08:03 +00:00
XCore