Hao Liu 19fdc268c3 Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions: ... sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshrun,sqshrn,uqshr,sqrshrn,uqrshrn,sshll,ushll and 4 convert instructions: scvtf,ucvtf,fcvtzs,fcvtzu git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189925 91177308-0d34-0410-b5e6-96231b3b80d8		2013-09-04 09:28:24 +00:00
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AArch64	Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions:	2013-09-04 09:28:24 +00:00
ARM	[ARMv8]	2013-08-28 16:39:20 +00:00
AsmParser
COFF
Disassembler	Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions:	2013-09-04 09:28:24 +00:00
ELF
MachO	The darwin integrated assembler for X86 in 64-bit mode is not rejecting	2013-08-29 00:19:03 +00:00
Markup
Mips	[mips] Use ptr_rc to simplify definitions of base+index load/store instructions.	2013-08-28 00:55:15 +00:00
PowerPC	Given target assembler parsers a chance to handle variant expressions	2013-08-27 20:23:19 +00:00
SystemZ	[SystemZ] Add support for TMHH, TMHL, TMLH and TMLL	2013-08-28 10:31:43 +00:00
X86	[ms-inline asm] Support offsets after segment registers	2013-08-27 21:56:17 +00:00