Asiri Rathnayake 3ad762170b Improvements to ARM assembler tests ... No functional changes. Got myself bitten in r223113 when adding support for modified immediate syntax (regressions reported by joerg@britannica.bec.de, fixes in r223366 and r223381). Our assembler tests did not cover serveral different syntax variants. This patch expands the test coverage to check for the following cases: 1. Modified immediate operands may be expressed with expressions, as in #(4 * 2) instead of #8. 2. Modified immediate operands may be _optionally_ prefixed by a '#' symbol or a '$' symbol. 3. Certain instructions (e.g. ADD) support single input register variants; [ADD r0, #mod_imm] is same as [ADD r0, r0, #mod_imm]. 4. Certain instructions have aliases which convert plain immediates to modified immediates. For an example, [ADD r0, -10] is not valid because -10 (in two's complement) cannot be encoded as a modified immediate, but ARMInstrInfo.td defines an alias which can transform this into a [SUB r0, 10]. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223475 91177308-0d34-0410-b5e6-96231b3b80d8		2014-12-05 16:33:56 +00:00
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AArch64
ARM	Improvements to ARM assembler tests	2014-12-05 16:33:56 +00:00
AsmParser
COFF
Disassembler	[Hexagon] Adding lit exception if Hexagon isn't built.	2014-12-04 04:28:38 +00:00
ELF	Commit back the correct bits of r222760 (was r222538).	2014-11-27 17:13:56 +00:00
Hexagon	[Hexagon] Adding cmp* immediate form instructions.	2014-11-26 19:43:12 +00:00
MachO
Markup
Mips	The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests.	2014-12-01 11:12:04 +00:00
PowerPC	[PowerPC] Add asm support for cache-inhibited ld/st instructions	2014-11-30 10:15:56 +00:00
R600
Sparc
SystemZ
X86	[X86][MC] Intel syntax: accept implicit memory operand sizes larger than 80.	2014-12-03 02:03:26 +00:00