llvm-6502/test/CodeGen
Logan Chien c8ecf53082 Refine the ARM EHABI test cases.
Since we have ARM unwind directive parser and assembler, we
can check the correctness in two stages:

1. From LLVM assembly (.ll) to ARM assembly (.s)
2. From ARM assembly (.s) to ELF object file (.o)

We already have several "*.s to *.o" test cases.  This CL adds
some "*.ll to *.s" test cases and removes the redundant "*.ll to *.o"
test cases.

New test cases to check "*.ll to *.s" code generator:

- ehabi.ll: Check the correctness of the generated unwind directives.
- section-name.ll: Check the section name of functions.

Removed test cases:

- ehabi-mc-cantunwind.ll
  (Covered by ehabi-cantunwind.ll, and eh-directive-cantunwind.s)
- ehabi-mc-compact-pr0.ll
  (Covered by ehabi.ll, eh-compact-pr0.s, eh-directive-save.s, and
   eh-directive-setfp.s)
- ehabi-mc-compact-pr1.ll
  (Covered by ehabi.ll, eh-compact-pr1.s, eh-directive-save.s, and
   eh-directive-setfp.s)
- ehabi-mc.ll
  (Covered by ehabi.ll, and eh-directive-integrated-test.s)
- ehabi-mc-section-group.ll
  (Covered by section-name.ll, and eh-directive-section-comdat.s)
- ehabi-mc-section.ll
  (Covered by section-name.ll, and eh-directive-section.s)
- ehabi-mc-sh_link.ll
  (Covered by eh-directive-text-section.s, and eh-directive-section.s)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183628 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-09 12:36:57 +00:00
..
AArch64 Change how we iterate over relocations on ELF. 2013-05-30 03:05:14 +00:00
ARM Refine the ARM EHABI test cases. 2013-06-09 12:36:57 +00:00
CPP
Generic Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen. 2013-05-21 14:37:16 +00:00
Hexagon Hexagon: Pass to replace tranfer/copy instructions into combine instruction 2013-05-14 18:54:06 +00:00
Inputs
MBlaze
Mips Teach AsmPrinter how to print odd constants. 2013-06-07 18:36:03 +00:00
MSP430 DAGCombiner: Simplify inverted bit tests 2013-05-08 06:44:42 +00:00
NVPTX [NVPTX] Re-enable support for virtual registers in the final output 2013-05-31 12:14:49 +00:00
PowerPC Disallow i64 div/rem in PPC32 counter loops 2013-06-07 22:16:19 +00:00
R600 R600: Anti dep better handled in tex clause 2013-06-07 23:30:26 +00:00
SI
SPARC [Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend. 2013-06-08 15:32:59 +00:00
SystemZ [SystemZ] Don't use LOAD and STORE REVERSED for volatile accesses 2013-05-31 13:25:22 +00:00
Thumb LocalStackSlotAllocation improvements 2013-04-30 20:04:37 +00:00
Thumb2 Cortex-R5 can issue Thumb2 integer division instructions. 2013-06-04 22:52:09 +00:00
X86 Removed PackedDouble domain from scalar instructions. Added more formats for the scalar stuff. 2013-06-09 07:37:10 +00:00
XCore [XCore] Fix handling of functions where only the LR is spilled. 2013-05-09 16:43:42 +00:00