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This patch introduces a new pass that computes the safe point to insert the prologue and epilogue of the function. The interest is to find safe points that are cheaper than the entry and exits blocks. As an example and to avoid regressions to be introduce, this patch also implements the required bits to enable the shrink-wrapping pass for AArch64. ** Context ** Currently we insert the prologue and epilogue of the method/function in the entry and exits blocks. Although this is correct, we can do a better job when those are not immediately required and insert them at less frequently executed places. The job of the shrink-wrapping pass is to identify such places. ** Motivating example ** Let us consider the following function that perform a call only in one branch of a if: define i32 @f(i32 %a, i32 %b) { %tmp = alloca i32, align 4 %tmp2 = icmp slt i32 %a, %b br i1 %tmp2, label %true, label %false true: store i32 %a, i32* %tmp, align 4 %tmp4 = call i32 @doSomething(i32 0, i32* %tmp) br label %false false: %tmp.0 = phi i32 [ %tmp4, %true ], [ %a, %0 ] ret i32 %tmp.0 } On AArch64 this code generates (removing the cfi directives to ease readabilities): _f: ; @f ; BB#0: stp x29, x30, [sp, #-16]! mov x29, sp sub sp, sp, #16 ; =16 cmp w0, w1 b.ge LBB0_2 ; BB#1: ; %true stur w0, [x29, #-4] sub x1, x29, #4 ; =4 mov w0, wzr bl _doSomething LBB0_2: ; %false mov sp, x29 ldp x29, x30, [sp], #16 ret With shrink-wrapping we could generate: _f: ; @f ; BB#0: cmp w0, w1 b.ge LBB0_2 ; BB#1: ; %true stp x29, x30, [sp, #-16]! mov x29, sp sub sp, sp, #16 ; =16 stur w0, [x29, #-4] sub x1, x29, #4 ; =4 mov w0, wzr bl _doSomething add sp, x29, #16 ; =16 ldp x29, x30, [sp], #16 LBB0_2: ; %false ret Therefore, we would pay the overhead of setting up/destroying the frame only if we actually do the call. ** Proposed Solution ** This patch introduces a new machine pass that perform the shrink-wrapping analysis (See the comments at the beginning of ShrinkWrap.cpp for more details). It then stores the safe save and restore point into the MachineFrameInfo attached to the MachineFunction. This information is then used by the PrologEpilogInserter (PEI) to place the related code at the right place. This pass runs right before the PEI. Unlike the original paper of Chow from PLDI’88, this implementation of shrink-wrapping does not use expensive data-flow analysis and does not need hack to properly avoid frequently executed point. Instead, it relies on dominance and loop properties. The pass is off by default and each target can opt-in by setting the EnableShrinkWrap boolean to true in their derived class of TargetPassConfig. This setting can also be overwritten on the command line by using -enable-shrink-wrap. Before you try out the pass for your target, make sure you properly fix your emitProlog/emitEpilog/adjustForXXX method to cope with basic blocks that are not necessarily the entry block. ** Design Decisions ** 1. ShrinkWrap is its own pass right now. It could frankly be merged into PEI but for debugging and clarity I thought it was best to have its own file. 2. Right now, we only support one save point and one restore point. At some point we can expand this to several save point and restore point, the impacted component would then be: - The pass itself: New algorithm needed. - MachineFrameInfo: Hold a list or set of Save/Restore point instead of one pointer. - PEI: Should loop over the save point and restore point. Anyhow, at least for this first iteration, I do not believe this is interesting to support the complex cases. We should revisit that when we motivating examples. Differential Revision: http://reviews.llvm.org/D9210 <rdar://problem/3201744> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236507 91177308-0d34-0410-b5e6-96231b3b80d8
105 lines
4.0 KiB
C++
105 lines
4.0 KiB
C++
//=- HexagonFrameLowering.h - Define frame lowering for Hexagon --*- C++ -*--=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H
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#define LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H
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#include "Hexagon.h"
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#include "llvm/Target/TargetFrameLowering.h"
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namespace llvm {
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class HexagonInstrInfo;
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class HexagonRegisterInfo;
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class HexagonFrameLowering : public TargetFrameLowering {
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public:
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explicit HexagonFrameLowering()
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: TargetFrameLowering(StackGrowsDown, 8, 0, 1, true) {}
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// All of the prolog/epilog functionality, including saving and restoring
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// callee-saved registers is handled in emitPrologue. This is to have the
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// logic for shrink-wrapping in one place.
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void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const
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override;
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
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override {}
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bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const override {
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return true;
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}
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bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const override {
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return true;
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}
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override;
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void processFunctionBeforeFrameFinalized(MachineFunction &MF,
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RegScavenger *RS = nullptr) const override;
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void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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RegScavenger *RS) const override;
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bool targetHandlesStackFrameRounding() const override {
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return true;
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}
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int getFrameIndexOffset(const MachineFunction &MF, int FI) const override;
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bool hasFP(const MachineFunction &MF) const override;
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const SpillSlot *getCalleeSavedSpillSlots(unsigned &NumEntries)
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const override {
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static const SpillSlot Offsets[] = {
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{ Hexagon::R17, -4 }, { Hexagon::R16, -8 }, { Hexagon::D8, -8 },
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{ Hexagon::R19, -12 }, { Hexagon::R18, -16 }, { Hexagon::D9, -16 },
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{ Hexagon::R21, -20 }, { Hexagon::R20, -24 }, { Hexagon::D10, -24 },
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{ Hexagon::R23, -28 }, { Hexagon::R22, -32 }, { Hexagon::D11, -32 },
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{ Hexagon::R25, -36 }, { Hexagon::R24, -40 }, { Hexagon::D12, -40 },
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{ Hexagon::R27, -44 }, { Hexagon::R26, -48 }, { Hexagon::D13, -48 }
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};
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NumEntries = array_lengthof(Offsets);
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return Offsets;
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}
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bool assignCalleeSavedSpillSlots(MachineFunction &MF,
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const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI)
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const override;
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bool needsAligna(const MachineFunction &MF) const;
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MachineInstr *getAlignaInstr(MachineFunction &MF) const;
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private:
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typedef std::vector<CalleeSavedInfo> CSIVect;
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void expandAlloca(MachineInstr *AI, const HexagonInstrInfo &TII,
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unsigned SP, unsigned CF) const;
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void insertPrologueInBlock(MachineBasicBlock &MBB) const;
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void insertEpilogueInBlock(MachineBasicBlock &MBB) const;
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bool insertCSRSpillsInBlock(MachineBasicBlock &MBB, const CSIVect &CSI,
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const HexagonRegisterInfo &HRI) const;
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bool insertCSRRestoresInBlock(MachineBasicBlock &MBB, const CSIVect &CSI,
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const HexagonRegisterInfo &HRI) const;
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void adjustForCalleeSavedRegsSpillCall(MachineFunction &MF) const;
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bool replacePredRegPseudoSpillCode(MachineFunction &MF) const;
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bool replaceVecPredRegPseudoSpillCode(MachineFunction &MF) const;
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void findShrunkPrologEpilog(MachineFunction &MF, MachineBasicBlock *&PrologB,
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MachineBasicBlock *&EpilogB) const;
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bool shouldInlineCSR(llvm::MachineFunction&, const CSIVect&) const;
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bool useSpillFunction(MachineFunction &MF, const CSIVect &CSI) const;
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bool useRestoreFunction(MachineFunction &MF, const CSIVect &CSI) const;
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};
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} // End llvm namespace
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#endif
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