mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-27 15:29:51 +00:00
Use a loop instruction with a constant extender for a hardware loop instruction that is too far away from the start of the loop. This is cheaper than changing the SA register value. Differential Revision: http://reviews.llvm.org/D9262 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235882 91177308-0d34-0410-b5e6-96231b3b80d8
509 lines
14 KiB
TableGen
509 lines
14 KiB
TableGen
//===- HexagonOperands.td - Hexagon immediate processing -*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illnois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// Immediate operands.
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let PrintMethod = "printImmOperand" in {
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// f32Ext type is used to identify constant extended floating point immediates.
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def f32Ext : Operand<f32>;
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def s32Imm : Operand<i32>;
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def s26_6Imm : Operand<i32>;
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def s16Imm : Operand<i32>;
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def s12Imm : Operand<i32>;
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def s11Imm : Operand<i32>;
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def s11_0Imm : Operand<i32>;
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def s11_1Imm : Operand<i32>;
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def s11_2Imm : Operand<i32>;
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def s11_3Imm : Operand<i32>;
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def s10Imm : Operand<i32>;
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def s9Imm : Operand<i32>;
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def m9Imm : Operand<i32>;
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def s8Imm : Operand<i32>;
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def s8Imm64 : Operand<i64>;
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def s6Imm : Operand<i32>;
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def s4Imm : Operand<i32>;
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def s4_0Imm : Operand<i32>;
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def s4_1Imm : Operand<i32>;
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def s4_2Imm : Operand<i32>;
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def s4_3Imm : Operand<i32>;
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def u64Imm : Operand<i64>;
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def u32Imm : Operand<i32>;
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def u26_6Imm : Operand<i32>;
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def u16Imm : Operand<i32>;
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def u16_0Imm : Operand<i32>;
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def u16_1Imm : Operand<i32>;
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def u16_2Imm : Operand<i32>;
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def u16_3Imm : Operand<i32>;
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def u11_3Imm : Operand<i32>;
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def u10Imm : Operand<i32>;
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def u9Imm : Operand<i32>;
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def u8Imm : Operand<i32>;
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def u7Imm : Operand<i32>;
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def u6Imm : Operand<i32>;
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def u6_0Imm : Operand<i32>;
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def u6_1Imm : Operand<i32>;
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def u6_2Imm : Operand<i32>;
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def u6_3Imm : Operand<i32>;
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def u5Imm : Operand<i32>;
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def u4Imm : Operand<i32>;
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def u3Imm : Operand<i32>;
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def u2Imm : Operand<i32>;
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def u1Imm : Operand<i32>;
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def n8Imm : Operand<i32>;
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def m6Imm : Operand<i32>;
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}
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let PrintMethod = "printNOneImmOperand" in
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def nOneImm : Operand<i32>;
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//
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// Immediate predicates
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//
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def s32ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isInt<32>(v);
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}]>;
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def s32_0ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isInt<32>(v);
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}]>;
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def s31_1ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedInt<31,1>(v);
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}]>;
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def s30_2ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedInt<31,1>(v);
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}]>;
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def s29_3ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedInt<31,1>(v);
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}]>;
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def s22_10ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedInt<22,10>(v);
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}]>;
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def s8_24ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedInt<8,24>(v);
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}]>;
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def s16_16ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedInt<16,16>(v);
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}]>;
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def s26_6ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedInt<26,6>(v);
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}]>;
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def s16ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isInt<16>(v);
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}]>;
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def s13ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isInt<13>(v);
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}]>;
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def s12ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isInt<12>(v);
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}]>;
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def s11_0ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isInt<11>(v);
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}]>;
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def s11_1ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedInt<11,1>(v);
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}]>;
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def s11_2ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedInt<11,2>(v);
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}]>;
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def s11_3ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedInt<11,3>(v);
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}]>;
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def s10ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isInt<10>(v);
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}]>;
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def s9ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isInt<9>(v);
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}]>;
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def m9ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isInt<9>(v) && (v != -256);
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}]>;
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def s8ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isInt<8>(v);
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}]>;
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def s8Imm64Pred : PatLeaf<(i64 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isInt<8>(v);
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}]>;
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def s6ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isInt<6>(v);
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}]>;
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def s4_0ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isInt<4>(v);
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}]>;
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def s4_1ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedInt<4,1>(v);
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}]>;
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def s4_2ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedInt<4,2>(v);
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}]>;
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def s4_3ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedInt<4,3>(v);
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}]>;
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def u64ImmPred : PatLeaf<(i64 imm), [{
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// Adding "N ||" to suppress gcc unused warning.
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return (N || true);
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}]>;
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def u32ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isUInt<32>(v);
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}]>;
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def u32_0ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isUInt<32>(v);
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}]>;
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def u31_1ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedUInt<31,1>(v);
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}]>;
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def u30_2ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedUInt<30,2>(v);
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}]>;
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def u29_3ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedUInt<29,3>(v);
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}]>;
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def u26_6ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedUInt<26,6>(v);
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}]>;
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def u16ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isUInt<16>(v);
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}]>;
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def u16_s8ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedUInt<16,8>(v);
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}]>;
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def u16_0ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isUInt<16>(v);
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}]>;
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def u11_3ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedUInt<11,3>(v);
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}]>;
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def u9ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isUInt<9>(v);
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}]>;
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def u8ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isUInt<8>(v);
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}]>;
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def u7StrictPosImmPred : ImmLeaf<i32, [{
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// u7StrictPosImmPred predicate - True if the immediate fits in an 7-bit
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// unsigned field and is strictly greater than 0.
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return isUInt<7>(Imm) && Imm > 0;
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}]>;
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def u7ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isUInt<7>(v);
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}]>;
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def u6ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isUInt<6>(v);
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}]>;
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def u6_0ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isUInt<6>(v);
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}]>;
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def u6_1ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedUInt<6,1>(v);
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}]>;
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def u6_2ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedUInt<6,2>(v);
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}]>;
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def u6_3ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedUInt<6,3>(v);
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}]>;
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def u5ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isUInt<5>(v);
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}]>;
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def u4ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isUInt<4>(v);
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}]>;
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def u3ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isUInt<3>(v);
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}]>;
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def u2ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isUInt<2>(v);
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}]>;
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def u1ImmPred : PatLeaf<(i1 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isUInt<1>(v);
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}]>;
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def m5BImmPred : PatLeaf<(i32 imm), [{
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// m5BImmPred predicate - True if the (char) number is in range -1 .. -31
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// and will fit in a 5 bit field when made positive, for use in memops.
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// this is specific to the zero extending of a negative by CombineInstr
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int8_t v = (int8_t)N->getSExtValue();
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return (-31 <= v && v <= -1);
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}]>;
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def m5HImmPred : PatLeaf<(i32 imm), [{
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// m5HImmPred predicate - True if the (short) number is in range -1 .. -31
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// and will fit in a 5 bit field when made positive, for use in memops.
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// this is specific to the zero extending of a negative by CombineInstr
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int16_t v = (int16_t)N->getSExtValue();
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return (-31 <= v && v <= -1);
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}]>;
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def m5ImmPred : PatLeaf<(i32 imm), [{
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// m5ImmPred predicate - True if the number is in range -1 .. -31
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// and will fit in a 5 bit field when made positive, for use in memops.
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int64_t v = (int64_t)N->getSExtValue();
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return (-31 <= v && v <= -1);
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}]>;
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//InN means negative integers in [-(2^N - 1), 0]
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def n8ImmPred : PatLeaf<(i32 imm), [{
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// n8ImmPred predicate - True if the immediate fits in a 8-bit signed
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// field.
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int64_t v = (int64_t)N->getSExtValue();
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return (-255 <= v && v <= 0);
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}]>;
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def nOneImmPred : PatLeaf<(i32 imm), [{
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// nOneImmPred predicate - True if the immediate is -1.
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int64_t v = (int64_t)N->getSExtValue();
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return (-1 == v);
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}]>;
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def Set5ImmPred : PatLeaf<(i32 imm), [{
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// Set5ImmPred predicate - True if the number is in the series of values.
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// [ 2^0, 2^1, ... 2^31 ]
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// For use in setbit immediate.
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uint32_t v = (int32_t)N->getSExtValue();
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// Constrain to 32 bits, and then check for single bit.
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return ImmIsSingleBit(v);
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}]>;
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def Clr5ImmPred : PatLeaf<(i32 imm), [{
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// Clr5ImmPred predicate - True if the number is in the series of
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// bit negated values.
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// [ 2^0, 2^1, ... 2^31 ]
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// For use in clrbit immediate.
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// Note: we are bit NOTing the value.
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uint32_t v = ~ (int32_t)N->getSExtValue();
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// Constrain to 32 bits, and then check for single bit.
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return ImmIsSingleBit(v);
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}]>;
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def SetClr5ImmPred : PatLeaf<(i32 imm), [{
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// SetClr5ImmPred predicate - True if the immediate is in range 0..31.
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int32_t v = (int32_t)N->getSExtValue();
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return (v >= 0 && v <= 31);
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}]>;
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def Set4ImmPred : PatLeaf<(i32 imm), [{
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// Set4ImmPred predicate - True if the number is in the series of values:
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// [ 2^0, 2^1, ... 2^15 ].
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// For use in setbit immediate.
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uint16_t v = (int16_t)N->getSExtValue();
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// Constrain to 16 bits, and then check for single bit.
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return ImmIsSingleBit(v);
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}]>;
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def Clr4ImmPred : PatLeaf<(i32 imm), [{
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// Clr4ImmPred predicate - True if the number is in the series of
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// bit negated values:
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// [ 2^0, 2^1, ... 2^15 ].
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// For use in setbit and clrbit immediate.
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uint16_t v = ~ (int16_t)N->getSExtValue();
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// Constrain to 16 bits, and then check for single bit.
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return ImmIsSingleBit(v);
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}]>;
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def SetClr4ImmPred : PatLeaf<(i32 imm), [{
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// SetClr4ImmPred predicate - True if the immediate is in the range 0..15.
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int16_t v = (int16_t)N->getSExtValue();
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return (v >= 0 && v <= 15);
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}]>;
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def Set3ImmPred : PatLeaf<(i32 imm), [{
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// Set3ImmPred predicate - True if the number is in the series of values:
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// [ 2^0, 2^1, ... 2^7 ].
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// For use in setbit immediate.
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uint8_t v = (int8_t)N->getSExtValue();
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// Constrain to 8 bits, and then check for single bit.
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return ImmIsSingleBit(v);
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}]>;
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def Clr3ImmPred : PatLeaf<(i32 imm), [{
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// Clr3ImmPred predicate - True if the number is in the series of
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// bit negated values:
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// [ 2^0, 2^1, ... 2^7 ].
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// For use in setbit and clrbit immediate.
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uint8_t v = ~ (int8_t)N->getSExtValue();
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// Constrain to 8 bits, and then check for single bit.
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return ImmIsSingleBit(v);
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}]>;
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def SetClr3ImmPred : PatLeaf<(i32 imm), [{
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// SetClr3ImmPred predicate - True if the immediate is in the range 0..7.
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int8_t v = (int8_t)N->getSExtValue();
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return (v >= 0 && v <= 7);
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}]>;
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// Extendable immediate operands.
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let PrintMethod = "printExtOperand" in {
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def s16Ext : Operand<i32>;
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def s12Ext : Operand<i32>;
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def s10Ext : Operand<i32>;
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def s9Ext : Operand<i32>;
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def s8Ext : Operand<i32>;
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def s6Ext : Operand<i32>;
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def s11_0Ext : Operand<i32>;
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def s11_1Ext : Operand<i32>;
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def s11_2Ext : Operand<i32>;
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def s11_3Ext : Operand<i32>;
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|
def u6Ext : Operand<i32>;
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|
def u7Ext : Operand<i32>;
|
|
def u8Ext : Operand<i32>;
|
|
def u9Ext : Operand<i32>;
|
|
def u10Ext : Operand<i32>;
|
|
def u6_0Ext : Operand<i32>;
|
|
def u6_1Ext : Operand<i32>;
|
|
def u6_2Ext : Operand<i32>;
|
|
def u6_3Ext : Operand<i32>;
|
|
}
|
|
|
|
|
|
// This complex pattern exists only to create a machine instruction operand
|
|
// of type "frame index". There doesn't seem to be a way to do that directly
|
|
// in the patterns.
|
|
def AddrFI : ComplexPattern<i32, 1, "SelectAddrFI", [frameindex], []>;
|
|
|
|
// These complex patterns are not strictly necessary, since global address
|
|
// folding will happen during DAG combining. For distinguishing between GA
|
|
// and GP, pat frags with HexagonCONST32 and HexagonCONST32_GP can be used.
|
|
def AddrGA : ComplexPattern<i32, 1, "SelectAddrGA", [], []>;
|
|
def AddrGP : ComplexPattern<i32, 1, "SelectAddrGP", [], []>;
|
|
|
|
// Address operands.
|
|
|
|
let PrintMethod = "printGlobalOperand" in {
|
|
def globaladdress : Operand<i32>;
|
|
def globaladdressExt : Operand<i32>;
|
|
}
|
|
|
|
let PrintMethod = "printJumpTable" in
|
|
def jumptablebase : Operand<i32>;
|
|
|
|
def brtarget : Operand<OtherVT>;
|
|
def brtargetExt : Operand<OtherVT> {
|
|
let PrintMethod = "printExtBrtarget";
|
|
}
|
|
def calltarget : Operand<i32>;
|
|
|
|
def bblabel : Operand<i32>;
|
|
def bbl : SDNode<"ISD::BasicBlock", SDTPtrLeaf , [], "BasicBlockSDNode">;
|
|
|
|
def symbolHi32 : Operand<i32> {
|
|
let PrintMethod = "printSymbolHi";
|
|
}
|
|
def symbolLo32 : Operand<i32> {
|
|
let PrintMethod = "printSymbolLo";
|
|
}
|
|
|
|
// Return true if for a 32 to 64-bit sign-extended load.
|
|
def is_sext_i32 : PatLeaf<(i64 DoubleRegs:$src1), [{
|
|
LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
|
|
if (!LD)
|
|
return false;
|
|
return LD->getExtensionType() == ISD::SEXTLOAD &&
|
|
LD->getMemoryVT().getScalarType() == MVT::i32;
|
|
}]>;
|