mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-01 19:29:22 +00:00
That's what it actually means, and with 16-bit support it's going to be a little more relevant since in a few corner cases we may actually want to distinguish between 16-bit and 32-bit mode (for example the bare 'push' aliases to pushw/pushl etc.) Patch by David Woodhouse git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197768 91177308-0d34-0410-b5e6-96231b3b80d8
63 lines
2.1 KiB
TableGen
63 lines
2.1 KiB
TableGen
//===-- X86InstrSVM.td - SVM Instruction Set Extension -----*- tablegen -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file describes the instructions that make up the AMD SVM instruction
|
|
// set.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// SVM instructions
|
|
|
|
// 0F 01 D9
|
|
def VMMCALL : I<0x01, MRM_D9, (outs), (ins), "vmmcall", []>, TB;
|
|
|
|
// 0F 01 DC
|
|
def STGI : I<0x01, MRM_DC, (outs), (ins), "stgi", []>, TB;
|
|
|
|
// 0F 01 DD
|
|
def CLGI : I<0x01, MRM_DD, (outs), (ins), "clgi", []>, TB;
|
|
|
|
// 0F 01 DE
|
|
let Uses = [EAX] in
|
|
def SKINIT : I<0x01, MRM_DE, (outs), (ins), "skinit\t{%eax|eax}", []>, TB;
|
|
|
|
// 0F 01 D8
|
|
let Uses = [EAX] in
|
|
def VMRUN32 : I<0x01, MRM_D8, (outs), (ins),
|
|
"vmrun\t{%eax|eax}", []>, TB, Requires<[Not64BitMode]>;
|
|
let Uses = [RAX] in
|
|
def VMRUN64 : I<0x01, MRM_D8, (outs), (ins),
|
|
"vmrun\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
|
|
|
|
// 0F 01 DA
|
|
let Uses = [EAX] in
|
|
def VMLOAD32 : I<0x01, MRM_DA, (outs), (ins),
|
|
"vmload\t{%eax|eax}", []>, TB, Requires<[Not64BitMode]>;
|
|
let Uses = [RAX] in
|
|
def VMLOAD64 : I<0x01, MRM_DA, (outs), (ins),
|
|
"vmload\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
|
|
|
|
// 0F 01 DB
|
|
let Uses = [EAX] in
|
|
def VMSAVE32 : I<0x01, MRM_DB, (outs), (ins),
|
|
"vmsave\t{%eax|eax}", []>, TB, Requires<[Not64BitMode]>;
|
|
let Uses = [RAX] in
|
|
def VMSAVE64 : I<0x01, MRM_DB, (outs), (ins),
|
|
"vmsave\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
|
|
|
|
// 0F 01 DF
|
|
let Uses = [EAX, ECX] in
|
|
def INVLPGA32 : I<0x01, MRM_DF, (outs), (ins),
|
|
"invlpga\t{%ecx, %eax|eax, ecx}", []>, TB, Requires<[Not64BitMode]>;
|
|
let Uses = [RAX, ECX] in
|
|
def INVLPGA64 : I<0x01, MRM_DF, (outs), (ins),
|
|
"invlpga\t{%ecx, %rax|rax, ecx}", []>, TB, Requires<[In64BitMode]>;
|
|
|