mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26497 91177308-0d34-0410-b5e6-96231b3b80d8
187 lines
6.1 KiB
C++
187 lines
6.1 KiB
C++
//===- TableGen.cpp - Top-Level TableGen implementation -------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// TableGen is a tool which can be used to build up a description of something,
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// then invoke one or more "tablegen backends" to emit information about the
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// description in some predefined format. In practice, this is used by the LLVM
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// code generators to automate generation of a code generator through a
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// high-level description of the target.
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//
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//===----------------------------------------------------------------------===//
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#include "Record.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/System/Signals.h"
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#include "llvm/Support/FileUtilities.h"
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#include "CodeEmitterGen.h"
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#include "RegisterInfoEmitter.h"
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#include "InstrInfoEmitter.h"
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#include "AsmWriterEmitter.h"
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#include "DAGISelEmitter.h"
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#include "SubtargetEmitter.h"
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#include "IntrinsicEmitter.h"
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#include <algorithm>
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#include <cstdio>
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#include <fstream>
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#include <ios>
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using namespace llvm;
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enum ActionType {
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PrintRecords,
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GenEmitter,
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GenRegisterEnums, GenRegister, GenRegisterHeader,
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GenInstrEnums, GenInstrs, GenAsmWriter,
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GenDAGISel,
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GenSubtarget,
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GenIntrinsic,
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PrintEnums
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};
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namespace {
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cl::opt<ActionType>
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Action(cl::desc("Action to perform:"),
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cl::values(clEnumValN(PrintRecords, "print-records",
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"Print all records to stdout (default)"),
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clEnumValN(GenEmitter, "gen-emitter",
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"Generate machine code emitter"),
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clEnumValN(GenRegisterEnums, "gen-register-enums",
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"Generate enum values for registers"),
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clEnumValN(GenRegister, "gen-register-desc",
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"Generate a register info description"),
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clEnumValN(GenRegisterHeader, "gen-register-desc-header",
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"Generate a register info description header"),
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clEnumValN(GenInstrEnums, "gen-instr-enums",
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"Generate enum values for instructions"),
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clEnumValN(GenInstrs, "gen-instr-desc",
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"Generate instruction descriptions"),
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clEnumValN(GenAsmWriter, "gen-asm-writer",
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"Generate assembly writer"),
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clEnumValN(GenDAGISel, "gen-dag-isel",
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"Generate a DAG instruction selector"),
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clEnumValN(GenSubtarget, "gen-subtarget",
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"Generate subtarget enumerations"),
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clEnumValN(GenIntrinsic, "gen-intrinsic",
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"Generate intrinsic information"),
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clEnumValN(PrintEnums, "print-enums",
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"Print enum values for a class"),
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clEnumValEnd));
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cl::opt<std::string>
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Class("class", cl::desc("Print Enum list for this class"),
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cl::value_desc("class name"));
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cl::opt<std::string>
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OutputFilename("o", cl::desc("Output filename"), cl::value_desc("filename"),
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cl::init("-"));
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cl::opt<std::string>
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InputFilename(cl::Positional, cl::desc("<input file>"), cl::init("-"));
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cl::list<std::string>
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IncludeDirs("I", cl::desc("Directory of include files"),
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cl::value_desc("directory"), cl::Prefix);
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}
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namespace llvm {
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void ParseFile(const std::string &Filename,
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const std::vector<std::string> &IncludeDirs);
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}
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RecordKeeper llvm::Records;
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int main(int argc, char **argv) {
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cl::ParseCommandLineOptions(argc, argv);
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ParseFile(InputFilename, IncludeDirs);
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std::ostream *Out = &std::cout;
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if (OutputFilename != "-") {
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Out = new std::ofstream(OutputFilename.c_str());
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if (!Out->good()) {
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std::cerr << argv[0] << ": error opening " << OutputFilename << "!\n";
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return 1;
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}
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// Make sure the file gets removed if *gasp* tablegen crashes...
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sys::RemoveFileOnSignal(sys::Path(OutputFilename));
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}
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try {
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switch (Action) {
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case PrintRecords:
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*Out << Records; // No argument, dump all contents
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break;
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case GenEmitter:
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CodeEmitterGen(Records).run(*Out);
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break;
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case GenRegisterEnums:
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RegisterInfoEmitter(Records).runEnums(*Out);
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break;
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case GenRegister:
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RegisterInfoEmitter(Records).run(*Out);
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break;
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case GenRegisterHeader:
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RegisterInfoEmitter(Records).runHeader(*Out);
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break;
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case GenInstrEnums:
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InstrInfoEmitter(Records).runEnums(*Out);
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break;
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case GenInstrs:
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InstrInfoEmitter(Records).run(*Out);
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break;
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case GenAsmWriter:
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AsmWriterEmitter(Records).run(*Out);
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break;
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case GenDAGISel:
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DAGISelEmitter(Records).run(*Out);
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break;
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case GenSubtarget:
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SubtargetEmitter(Records).run(*Out);
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break;
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case GenIntrinsic:
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IntrinsicEmitter(Records).run(*Out);
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break;
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case PrintEnums:
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{
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std::vector<Record*> Recs = Records.getAllDerivedDefinitions(Class);
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for (unsigned i = 0, e = Recs.size(); i != e; ++i)
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*Out << Recs[i]->getName() << ", ";
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*Out << "\n";
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break;
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}
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default:
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assert(1 && "Invalid Action");
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return 1;
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}
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} catch (const std::string &Error) {
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std::cerr << argv[0] << ": " << Error << "\n";
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if (Out != &std::cout) {
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delete Out; // Close the file
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std::remove(OutputFilename.c_str()); // Remove the file, it's broken
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}
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return 1;
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} catch (...) {
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std::cerr << argv[0] << ": Unknown unexpected exception occurred.\n";
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if (Out != &std::cout) {
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delete Out; // Close the file
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std::remove(OutputFilename.c_str()); // Remove the file, it's broken
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}
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return 2;
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}
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if (Out != &std::cout) {
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delete Out; // Close the file
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}
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return 0;
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}
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