llvm-6502/lib/Target/AArch64
Jim Grosbach 05bb7c5045 AArch64: Better codegen for loading from __fp16.
Loading will generally extend to an f32 or an 64, so make sure
to match those patterns directly to load into the FPR16 register
class directly rather than going through the integer GPRs.

This also eliminates an extra step in the convert-to-f64 path
which was first converting to f32 and then to f64 from there.

rdar://17594379

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212573 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-08 23:28:48 +00:00
..
AsmParser Truncate the immediate in logical operation to the register width 2014-07-08 09:53:04 +00:00
Disassembler
InstPrinter
MCTargetDesc
TargetInfo
Utils
AArch64.h
AArch64.td
AArch64AddressTypePromotion.cpp AArch64: Re-enable AArch64AddressTypePromotion 2014-07-02 18:17:40 +00:00
AArch64AdvSIMDScalarPass.cpp
AArch64AsmPrinter.cpp
AArch64BranchRelaxation.cpp
AArch64CallingConvention.td
AArch64CleanupLocalDynamicTLSPass.cpp
AArch64CollectLOH.cpp
AArch64ConditionalCompares.cpp
AArch64DeadRegisterDefinitionsPass.cpp
AArch64ExpandPseudoInsts.cpp
AArch64FastISel.cpp Allow AArch64FastISel to degrade graceully in the presence of an MVT::i128 2014-07-07 21:37:51 +00:00
AArch64FrameLowering.cpp
AArch64FrameLowering.h
AArch64InstrAtomics.td
AArch64InstrFormats.td
AArch64InstrInfo.cpp
AArch64InstrInfo.h
AArch64InstrInfo.td AArch64: Better codegen for loading from __fp16. 2014-07-08 23:28:48 +00:00
AArch64ISelDAGToDAG.cpp [AArch64] Unsized types don't specify an alignment. 2014-06-30 15:03:00 +00:00
AArch64ISelLowering.cpp [AArch64] Normalize all constants to build a vector. 2014-07-07 02:45:40 +00:00
AArch64ISelLowering.h [codegen,aarch64] Add a target hook to the code generator to control 2014-07-03 00:23:43 +00:00
AArch64LoadStoreOptimizer.cpp
AArch64MachineFunctionInfo.h
AArch64MCInstLower.cpp
AArch64MCInstLower.h
AArch64PerfectShuffle.h
AArch64PromoteConstant.cpp
AArch64RegisterInfo.cpp
AArch64RegisterInfo.h
AArch64RegisterInfo.td
AArch64SchedA53.td
AArch64SchedA57.td
AArch64SchedA57WriteRes.td
AArch64SchedCyclone.td
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp [DAG] Pass the argument list to the CallLoweringInfo via move semantics. NFCI. 2014-07-01 22:01:54 +00:00
AArch64SelectionDAGInfo.h
AArch64StorePairSuppress.cpp
AArch64Subtarget.cpp
AArch64Subtarget.h
AArch64TargetMachine.cpp AArch64: Re-enable AArch64AddressTypePromotion 2014-07-02 18:17:40 +00:00
AArch64TargetMachine.h Remove extraneous includes from the target machines. 2014-06-26 19:30:05 +00:00
AArch64TargetObjectFile.cpp
AArch64TargetObjectFile.h
AArch64TargetTransformInfo.cpp
CMakeLists.txt
LLVMBuild.txt
Makefile