llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-30 21:29:28 +00:00

History

Jakob Stoklund Olesen f28987b76e Use set operations instead of plain lists to enumerate register classes. This simplifies many of the target description files since it is common for register classes to be related or contain sequences of numbered registers. I have verified that this doesn't change the files generated by TableGen for ARM and X86. It alters the allocation order of MBlaze GPR and Mips FGR32 registers, but I believe the change is benign. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133105 91177308-0d34-0410-b5e6-96231b3b80d8		2011-06-15 23:28:14 +00:00
..
TargetInfo
Alpha.h
Alpha.td
AlphaAsmPrinter.cpp
AlphaBranchSelector.cpp
AlphaCallingConv.td
AlphaFrameLowering.cpp
AlphaFrameLowering.h
AlphaInstrFormats.td
AlphaInstrInfo.cpp
AlphaInstrInfo.h
AlphaInstrInfo.td
AlphaISelDAGToDAG.cpp
AlphaISelLowering.cpp	Add a parameter to CCState so that it can access the MachineFunction.	2011-06-08 23:55:35 +00:00
AlphaISelLowering.h	Make the logic for determining function alignment more explicit. No functionality change.	2011-05-06 20:34:06 +00:00
AlphaLLRP.cpp
AlphaMachineFunctionInfo.h
AlphaMCAsmInfo.cpp
AlphaMCAsmInfo.h
AlphaRegisterInfo.cpp	Use the dwarf->llvm mapping to print register names in the cfi	2011-05-30 20:20:15 +00:00
AlphaRegisterInfo.h	Use the dwarf->llvm mapping to print register names in the cfi	2011-05-30 20:20:15 +00:00
AlphaRegisterInfo.td	Use set operations instead of plain lists to enumerate register classes.	2011-06-15 23:28:14 +00:00
AlphaRelocations.h
AlphaSchedule.td
AlphaSelectionDAGInfo.cpp
AlphaSelectionDAGInfo.h
AlphaSubtarget.cpp
AlphaSubtarget.h
AlphaTargetMachine.cpp
AlphaTargetMachine.h
CMakeLists.txt
Makefile
README.txt

README.txt

***

add gcc builtins for alpha instructions


***

custom expand byteswap into nifty 
extract/insert/mask byte/word/longword/quadword low/high
sequences

***

see if any of the extract/insert/mask operations can be added

***

match more interesting things for cmovlbc cmovlbs (move if low bit clear/set)

***

lower srem and urem

remq(i,j):  i - (j * divq(i,j)) if j != 0
remqu(i,j): i - (j * divqu(i,j)) if j != 0
reml(i,j):  i - (j * divl(i,j)) if j != 0
remlu(i,j): i - (j * divlu(i,j)) if j != 0

***

add crazy vector instructions (MVI):

(MIN|MAX)(U|S)(B8|W4) min and max, signed and unsigned, byte and word
PKWB, UNPKBW pack/unpack word to byte
PKLB UNPKBL pack/unpack long to byte
PERR pixel error (sum across bytes of bytewise abs(i8v8 a - i8v8 b))

cmpbytes bytewise cmpeq of i8v8 a and i8v8 b (not part of MVI extensions)

this has some good examples for other operations that can be synthesised well 
from these rather meager vector ops (such as saturating add).
http://www.alphalinux.org/docs/MVI-full.html