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https://github.com/c64scene-ar/llvm-6502.git
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We've been performing the wrong operation on ARM for "atomicrmw nand" for years, since "a NAND b" is "~(a & b)" rather than ARM's very tempting "a & ~b". This bled over into the generic expansion pass. So I assume no-one has ever actually tried to do an atomic nand in the real world. Oh well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212443 91177308-0d34-0410-b5e6-96231b3b80d8
381 lines
14 KiB
C++
381 lines
14 KiB
C++
//===-- AtomicExpandLoadLinkedPass.cpp - Expand atomic instructions -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a pass (at IR level) to replace atomic instructions with
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// appropriate (intrinsic-based) ldrex/strex loops.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/IR/Module.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "arm-atomic-expand"
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namespace {
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class AtomicExpandLoadLinked : public FunctionPass {
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const TargetMachine *TM;
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public:
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static char ID; // Pass identification, replacement for typeid
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explicit AtomicExpandLoadLinked(const TargetMachine *TM = nullptr)
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: FunctionPass(ID), TM(TM) {
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initializeAtomicExpandLoadLinkedPass(*PassRegistry::getPassRegistry());
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}
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bool runOnFunction(Function &F) override;
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bool expandAtomicInsts(Function &F);
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bool expandAtomicLoad(LoadInst *LI);
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bool expandAtomicStore(StoreInst *LI);
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bool expandAtomicRMW(AtomicRMWInst *AI);
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bool expandAtomicCmpXchg(AtomicCmpXchgInst *CI);
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AtomicOrdering insertLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord);
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void insertTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord);
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};
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}
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char AtomicExpandLoadLinked::ID = 0;
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char &llvm::AtomicExpandLoadLinkedID = AtomicExpandLoadLinked::ID;
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INITIALIZE_TM_PASS(AtomicExpandLoadLinked, "atomic-ll-sc",
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"Expand Atomic calls in terms of load-linked & store-conditional",
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false, false)
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FunctionPass *llvm::createAtomicExpandLoadLinkedPass(const TargetMachine *TM) {
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return new AtomicExpandLoadLinked(TM);
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}
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bool AtomicExpandLoadLinked::runOnFunction(Function &F) {
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if (!TM || !TM->getSubtargetImpl()->enableAtomicExpandLoadLinked())
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return false;
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SmallVector<Instruction *, 1> AtomicInsts;
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// Changing control-flow while iterating through it is a bad idea, so gather a
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// list of all atomic instructions before we start.
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for (BasicBlock &BB : F)
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for (Instruction &Inst : BB) {
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if (isa<AtomicRMWInst>(&Inst) || isa<AtomicCmpXchgInst>(&Inst) ||
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(isa<LoadInst>(&Inst) && cast<LoadInst>(&Inst)->isAtomic()) ||
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(isa<StoreInst>(&Inst) && cast<StoreInst>(&Inst)->isAtomic()))
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AtomicInsts.push_back(&Inst);
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}
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bool MadeChange = false;
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for (Instruction *Inst : AtomicInsts) {
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if (!TM->getTargetLowering()->shouldExpandAtomicInIR(Inst))
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continue;
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if (AtomicRMWInst *AI = dyn_cast<AtomicRMWInst>(Inst))
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MadeChange |= expandAtomicRMW(AI);
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else if (AtomicCmpXchgInst *CI = dyn_cast<AtomicCmpXchgInst>(Inst))
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MadeChange |= expandAtomicCmpXchg(CI);
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else if (LoadInst *LI = dyn_cast<LoadInst>(Inst))
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MadeChange |= expandAtomicLoad(LI);
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else if (StoreInst *SI = dyn_cast<StoreInst>(Inst))
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MadeChange |= expandAtomicStore(SI);
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else
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llvm_unreachable("Unknown atomic instruction");
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}
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return MadeChange;
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}
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bool AtomicExpandLoadLinked::expandAtomicLoad(LoadInst *LI) {
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// Load instructions don't actually need a leading fence, even in the
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// SequentiallyConsistent case.
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AtomicOrdering MemOpOrder =
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TM->getTargetLowering()->getInsertFencesForAtomic() ? Monotonic
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: LI->getOrdering();
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// The only 64-bit load guaranteed to be single-copy atomic by the ARM ARM is
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// an ldrexd (A3.5.3).
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IRBuilder<> Builder(LI);
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Value *Val = TM->getTargetLowering()->emitLoadLinked(
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Builder, LI->getPointerOperand(), MemOpOrder);
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insertTrailingFence(Builder, LI->getOrdering());
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LI->replaceAllUsesWith(Val);
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LI->eraseFromParent();
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return true;
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}
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bool AtomicExpandLoadLinked::expandAtomicStore(StoreInst *SI) {
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// The only atomic 64-bit store on ARM is an strexd that succeeds, which means
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// we need a loop and the entire instruction is essentially an "atomicrmw
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// xchg" that ignores the value loaded.
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IRBuilder<> Builder(SI);
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AtomicRMWInst *AI =
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Builder.CreateAtomicRMW(AtomicRMWInst::Xchg, SI->getPointerOperand(),
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SI->getValueOperand(), SI->getOrdering());
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SI->eraseFromParent();
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// Now we have an appropriate swap instruction, lower it as usual.
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return expandAtomicRMW(AI);
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}
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bool AtomicExpandLoadLinked::expandAtomicRMW(AtomicRMWInst *AI) {
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AtomicOrdering Order = AI->getOrdering();
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Value *Addr = AI->getPointerOperand();
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BasicBlock *BB = AI->getParent();
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Function *F = BB->getParent();
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LLVMContext &Ctx = F->getContext();
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// Given: atomicrmw some_op iN* %addr, iN %incr ordering
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//
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// The standard expansion we produce is:
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// [...]
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// fence?
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// atomicrmw.start:
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// %loaded = @load.linked(%addr)
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// %new = some_op iN %loaded, %incr
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// %stored = @store_conditional(%new, %addr)
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// %try_again = icmp i32 ne %stored, 0
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// br i1 %try_again, label %loop, label %atomicrmw.end
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// atomicrmw.end:
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// fence?
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// [...]
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BasicBlock *ExitBB = BB->splitBasicBlock(AI, "atomicrmw.end");
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BasicBlock *LoopBB = BasicBlock::Create(Ctx, "atomicrmw.start", F, ExitBB);
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// This grabs the DebugLoc from AI.
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IRBuilder<> Builder(AI);
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// The split call above "helpfully" added a branch at the end of BB (to the
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// wrong place), but we might want a fence too. It's easiest to just remove
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// the branch entirely.
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std::prev(BB->end())->eraseFromParent();
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Builder.SetInsertPoint(BB);
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AtomicOrdering MemOpOrder = insertLeadingFence(Builder, Order);
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Builder.CreateBr(LoopBB);
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// Start the main loop block now that we've taken care of the preliminaries.
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Builder.SetInsertPoint(LoopBB);
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Value *Loaded =
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TM->getTargetLowering()->emitLoadLinked(Builder, Addr, MemOpOrder);
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Value *NewVal;
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switch (AI->getOperation()) {
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case AtomicRMWInst::Xchg:
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NewVal = AI->getValOperand();
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break;
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case AtomicRMWInst::Add:
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NewVal = Builder.CreateAdd(Loaded, AI->getValOperand(), "new");
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break;
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case AtomicRMWInst::Sub:
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NewVal = Builder.CreateSub(Loaded, AI->getValOperand(), "new");
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break;
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case AtomicRMWInst::And:
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NewVal = Builder.CreateAnd(Loaded, AI->getValOperand(), "new");
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break;
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case AtomicRMWInst::Nand:
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NewVal = Builder.CreateNot(Builder.CreateAnd(Loaded, AI->getValOperand()),
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"new");
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break;
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case AtomicRMWInst::Or:
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NewVal = Builder.CreateOr(Loaded, AI->getValOperand(), "new");
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break;
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case AtomicRMWInst::Xor:
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NewVal = Builder.CreateXor(Loaded, AI->getValOperand(), "new");
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break;
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case AtomicRMWInst::Max:
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NewVal = Builder.CreateICmpSGT(Loaded, AI->getValOperand());
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NewVal = Builder.CreateSelect(NewVal, Loaded, AI->getValOperand(), "new");
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break;
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case AtomicRMWInst::Min:
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NewVal = Builder.CreateICmpSLE(Loaded, AI->getValOperand());
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NewVal = Builder.CreateSelect(NewVal, Loaded, AI->getValOperand(), "new");
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break;
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case AtomicRMWInst::UMax:
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NewVal = Builder.CreateICmpUGT(Loaded, AI->getValOperand());
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NewVal = Builder.CreateSelect(NewVal, Loaded, AI->getValOperand(), "new");
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break;
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case AtomicRMWInst::UMin:
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NewVal = Builder.CreateICmpULE(Loaded, AI->getValOperand());
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NewVal = Builder.CreateSelect(NewVal, Loaded, AI->getValOperand(), "new");
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break;
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default:
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llvm_unreachable("Unknown atomic op");
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}
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Value *StoreSuccess = TM->getTargetLowering()->emitStoreConditional(
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Builder, NewVal, Addr, MemOpOrder);
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Value *TryAgain = Builder.CreateICmpNE(
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StoreSuccess, ConstantInt::get(IntegerType::get(Ctx, 32), 0), "tryagain");
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Builder.CreateCondBr(TryAgain, LoopBB, ExitBB);
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Builder.SetInsertPoint(ExitBB, ExitBB->begin());
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insertTrailingFence(Builder, Order);
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AI->replaceAllUsesWith(Loaded);
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AI->eraseFromParent();
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return true;
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}
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bool AtomicExpandLoadLinked::expandAtomicCmpXchg(AtomicCmpXchgInst *CI) {
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AtomicOrdering SuccessOrder = CI->getSuccessOrdering();
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AtomicOrdering FailureOrder = CI->getFailureOrdering();
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Value *Addr = CI->getPointerOperand();
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BasicBlock *BB = CI->getParent();
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Function *F = BB->getParent();
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LLVMContext &Ctx = F->getContext();
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// Given: cmpxchg some_op iN* %addr, iN %desired, iN %new success_ord fail_ord
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//
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// The full expansion we produce is:
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// [...]
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// fence?
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// cmpxchg.start:
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// %loaded = @load.linked(%addr)
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// %should_store = icmp eq %loaded, %desired
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// br i1 %should_store, label %cmpxchg.trystore,
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// label %cmpxchg.failure
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// cmpxchg.trystore:
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// %stored = @store_conditional(%new, %addr)
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// %success = icmp eq i32 %stored, 0
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// br i1 %success, label %cmpxchg.success, label %loop/%cmpxchg.failure
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// cmpxchg.success:
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// fence?
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// br label %cmpxchg.end
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// cmpxchg.failure:
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// fence?
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// br label %cmpxchg.end
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// cmpxchg.end:
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// %success = phi i1 [true, %cmpxchg.success], [false, %cmpxchg.failure]
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// %restmp = insertvalue { iN, i1 } undef, iN %loaded, 0
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// %res = insertvalue { iN, i1 } %restmp, i1 %success, 1
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// [...]
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BasicBlock *ExitBB = BB->splitBasicBlock(CI, "cmpxchg.end");
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auto FailureBB = BasicBlock::Create(Ctx, "cmpxchg.failure", F, ExitBB);
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auto SuccessBB = BasicBlock::Create(Ctx, "cmpxchg.success", F, FailureBB);
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auto TryStoreBB = BasicBlock::Create(Ctx, "cmpxchg.trystore", F, SuccessBB);
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auto LoopBB = BasicBlock::Create(Ctx, "cmpxchg.start", F, TryStoreBB);
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// This grabs the DebugLoc from CI
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IRBuilder<> Builder(CI);
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// The split call above "helpfully" added a branch at the end of BB (to the
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// wrong place), but we might want a fence too. It's easiest to just remove
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// the branch entirely.
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std::prev(BB->end())->eraseFromParent();
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Builder.SetInsertPoint(BB);
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AtomicOrdering MemOpOrder = insertLeadingFence(Builder, SuccessOrder);
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Builder.CreateBr(LoopBB);
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// Start the main loop block now that we've taken care of the preliminaries.
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Builder.SetInsertPoint(LoopBB);
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Value *Loaded =
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TM->getTargetLowering()->emitLoadLinked(Builder, Addr, MemOpOrder);
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Value *ShouldStore =
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Builder.CreateICmpEQ(Loaded, CI->getCompareOperand(), "should_store");
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// If the the cmpxchg doesn't actually need any ordering when it fails, we can
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// jump straight past that fence instruction (if it exists).
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Builder.CreateCondBr(ShouldStore, TryStoreBB, FailureBB);
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Builder.SetInsertPoint(TryStoreBB);
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Value *StoreSuccess = TM->getTargetLowering()->emitStoreConditional(
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Builder, CI->getNewValOperand(), Addr, MemOpOrder);
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StoreSuccess = Builder.CreateICmpEQ(
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StoreSuccess, ConstantInt::get(Type::getInt32Ty(Ctx), 0), "success");
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Builder.CreateCondBr(StoreSuccess, SuccessBB,
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CI->isWeak() ? FailureBB : LoopBB);
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// Make sure later instructions don't get reordered with a fence if necessary.
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Builder.SetInsertPoint(SuccessBB);
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insertTrailingFence(Builder, SuccessOrder);
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Builder.CreateBr(ExitBB);
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Builder.SetInsertPoint(FailureBB);
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insertTrailingFence(Builder, FailureOrder);
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Builder.CreateBr(ExitBB);
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// Finally, we have control-flow based knowledge of whether the cmpxchg
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// succeeded or not. We expose this to later passes by converting any
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// subsequent "icmp eq/ne %loaded, %oldval" into a use of an appropriate PHI.
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// Setup the builder so we can create any PHIs we need.
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Builder.SetInsertPoint(ExitBB, ExitBB->begin());
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PHINode *Success = Builder.CreatePHI(Type::getInt1Ty(Ctx), 2);
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Success->addIncoming(ConstantInt::getTrue(Ctx), SuccessBB);
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Success->addIncoming(ConstantInt::getFalse(Ctx), FailureBB);
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// Look for any users of the cmpxchg that are just comparing the loaded value
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// against the desired one, and replace them with the CFG-derived version.
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SmallVector<ExtractValueInst *, 2> PrunedInsts;
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for (auto User : CI->users()) {
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ExtractValueInst *EV = dyn_cast<ExtractValueInst>(User);
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if (!EV)
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continue;
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assert(EV->getNumIndices() == 1 && EV->getIndices()[0] <= 1 &&
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"weird extraction from { iN, i1 }");
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if (EV->getIndices()[0] == 0)
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EV->replaceAllUsesWith(Loaded);
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else
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EV->replaceAllUsesWith(Success);
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PrunedInsts.push_back(EV);
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}
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// We can remove the instructions now we're no longer iterating through them.
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for (auto EV : PrunedInsts)
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EV->eraseFromParent();
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if (!CI->use_empty()) {
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// Some use of the full struct return that we don't understand has happened,
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// so we've got to reconstruct it properly.
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Value *Res;
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Res = Builder.CreateInsertValue(UndefValue::get(CI->getType()), Loaded, 0);
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Res = Builder.CreateInsertValue(Res, Success, 1);
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CI->replaceAllUsesWith(Res);
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}
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CI->eraseFromParent();
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return true;
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}
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AtomicOrdering AtomicExpandLoadLinked::insertLeadingFence(IRBuilder<> &Builder,
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AtomicOrdering Ord) {
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if (!TM->getTargetLowering()->getInsertFencesForAtomic())
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return Ord;
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if (Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent)
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Builder.CreateFence(Release);
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// The exclusive operations don't need any barrier if we're adding separate
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// fences.
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return Monotonic;
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}
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void AtomicExpandLoadLinked::insertTrailingFence(IRBuilder<> &Builder,
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AtomicOrdering Ord) {
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if (!TM->getTargetLowering()->getInsertFencesForAtomic())
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return;
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if (Ord == Acquire || Ord == AcquireRelease)
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Builder.CreateFence(Acquire);
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else if (Ord == SequentiallyConsistent)
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Builder.CreateFence(SequentiallyConsistent);
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}
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