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This removes static initializers from the backends which generate this data, and also makes this struct match the other Tablegen generated structs in behaviour Reviewed by Andy Trick and Chandler C git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216919 91177308-0d34-0410-b5e6-96231b3b80d8
436 lines
18 KiB
C++
436 lines
18 KiB
C++
//===---- MachineCombiner.cpp - Instcombining on SSA form machine code ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// The machine combiner pass uses machine trace metrics to ensure the combined
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// instructions does not lengthen the critical path or the resource depth.
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "machine-combiner"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineTraceMetrics.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetSchedule.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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using namespace llvm;
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STATISTIC(NumInstCombined, "Number of machineinst combined");
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namespace {
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class MachineCombiner : public MachineFunctionPass {
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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MCSchedModel SchedModel;
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MachineRegisterInfo *MRI;
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MachineTraceMetrics *Traces;
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MachineTraceMetrics::Ensemble *MinInstr;
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TargetSchedModel TSchedModel;
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/// OptSize - True if optimizing for code size.
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bool OptSize;
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public:
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static char ID;
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MachineCombiner() : MachineFunctionPass(ID) {
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initializeMachineCombinerPass(*PassRegistry::getPassRegistry());
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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bool runOnMachineFunction(MachineFunction &MF) override;
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const char *getPassName() const override { return "Machine InstCombiner"; }
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private:
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bool doSubstitute(unsigned NewSize, unsigned OldSize);
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bool combineInstructions(MachineBasicBlock *);
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MachineInstr *getOperandDef(const MachineOperand &MO);
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unsigned getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs,
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DenseMap<unsigned, unsigned> &InstrIdxForVirtReg,
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MachineTraceMetrics::Trace BlockTrace);
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unsigned getLatency(MachineInstr *Root, MachineInstr *NewRoot,
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MachineTraceMetrics::Trace BlockTrace);
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bool
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preservesCriticalPathLen(MachineBasicBlock *MBB, MachineInstr *Root,
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MachineTraceMetrics::Trace BlockTrace,
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SmallVectorImpl<MachineInstr *> &InsInstrs,
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DenseMap<unsigned, unsigned> &InstrIdxForVirtReg);
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bool preservesResourceLen(MachineBasicBlock *MBB,
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MachineTraceMetrics::Trace BlockTrace,
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SmallVectorImpl<MachineInstr *> &InsInstrs,
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SmallVectorImpl<MachineInstr *> &DelInstrs);
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void instr2instrSC(SmallVectorImpl<MachineInstr *> &Instrs,
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SmallVectorImpl<const MCSchedClassDesc *> &InstrsSC);
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};
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}
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char MachineCombiner::ID = 0;
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char &llvm::MachineCombinerID = MachineCombiner::ID;
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INITIALIZE_PASS_BEGIN(MachineCombiner, "machine-combiner",
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"Machine InstCombiner", false, false)
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INITIALIZE_PASS_DEPENDENCY(MachineTraceMetrics)
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INITIALIZE_PASS_END(MachineCombiner, "machine-combiner", "Machine InstCombiner",
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false, false)
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void MachineCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addPreserved<MachineDominatorTree>();
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AU.addPreserved<MachineLoopInfo>();
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AU.addRequired<MachineTraceMetrics>();
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AU.addPreserved<MachineTraceMetrics>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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MachineInstr *MachineCombiner::getOperandDef(const MachineOperand &MO) {
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MachineInstr *DefInstr = nullptr;
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// We need a virtual register definition.
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if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
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DefInstr = MRI->getUniqueVRegDef(MO.getReg());
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// PHI's have no depth etc.
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if (DefInstr && DefInstr->isPHI())
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DefInstr = nullptr;
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return DefInstr;
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}
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/// getDepth - Computes depth of instructions in vector \InsInstr.
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///
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/// \param InsInstrs is a vector of machine instructions
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/// \param InstrIdxForVirtReg is a dense map of virtual register to index
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/// of defining machine instruction in \p InsInstrs
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/// \param BlockTrace is a trace of machine instructions
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///
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/// \returns Depth of last instruction in \InsInstrs ("NewRoot")
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unsigned
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MachineCombiner::getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs,
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DenseMap<unsigned, unsigned> &InstrIdxForVirtReg,
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MachineTraceMetrics::Trace BlockTrace) {
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SmallVector<unsigned, 16> InstrDepth;
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assert(TSchedModel.hasInstrSchedModel() && "Missing machine model\n");
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// Foreach instruction in in the new sequence compute the depth based on the
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// operands. Use the trace information when possible. For new operands which
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// are tracked in the InstrIdxForVirtReg map depth is looked up in InstrDepth
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for (auto *InstrPtr : InsInstrs) { // for each Use
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unsigned IDepth = 0;
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DEBUG(dbgs() << "NEW INSTR "; InstrPtr->dump(); dbgs() << "\n";);
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for (unsigned i = 0, e = InstrPtr->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = InstrPtr->getOperand(i);
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// Check for virtual register operand.
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if (!(MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())))
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continue;
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if (!MO.isUse())
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continue;
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unsigned DepthOp = 0;
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unsigned LatencyOp = 0;
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DenseMap<unsigned, unsigned>::iterator II =
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InstrIdxForVirtReg.find(MO.getReg());
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if (II != InstrIdxForVirtReg.end()) {
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// Operand is new virtual register not in trace
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assert(II->second < InstrDepth.size() && "Bad Index");
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MachineInstr *DefInstr = InsInstrs[II->second];
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assert(DefInstr &&
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"There must be a definition for a new virtual register");
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DepthOp = InstrDepth[II->second];
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LatencyOp = TSchedModel.computeOperandLatency(
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DefInstr, DefInstr->findRegisterDefOperandIdx(MO.getReg()),
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InstrPtr, InstrPtr->findRegisterUseOperandIdx(MO.getReg()));
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} else {
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MachineInstr *DefInstr = getOperandDef(MO);
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if (DefInstr) {
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DepthOp = BlockTrace.getInstrCycles(DefInstr).Depth;
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LatencyOp = TSchedModel.computeOperandLatency(
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DefInstr, DefInstr->findRegisterDefOperandIdx(MO.getReg()),
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InstrPtr, InstrPtr->findRegisterUseOperandIdx(MO.getReg()));
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}
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}
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IDepth = std::max(IDepth, DepthOp + LatencyOp);
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}
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InstrDepth.push_back(IDepth);
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}
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unsigned NewRootIdx = InsInstrs.size() - 1;
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return InstrDepth[NewRootIdx];
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}
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/// getLatency - Computes instruction latency as max of latency of defined
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/// operands
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///
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/// \param Root is a machine instruction that could be replaced by NewRoot.
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/// It is used to compute a more accurate latency information for NewRoot in
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/// case there is a dependent instruction in the same trace (\p BlockTrace)
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/// \param NewRoot is the instruction for which the latency is computed
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/// \param BlockTrace is a trace of machine instructions
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///
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/// \returns Latency of \p NewRoot
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unsigned MachineCombiner::getLatency(MachineInstr *Root, MachineInstr *NewRoot,
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MachineTraceMetrics::Trace BlockTrace) {
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assert(TSchedModel.hasInstrSchedModel() && "Missing machine model\n");
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// Check each definition in NewRoot and compute the latency
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unsigned NewRootLatency = 0;
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for (unsigned i = 0, e = NewRoot->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = NewRoot->getOperand(i);
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// Check for virtual register operand.
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if (!(MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())))
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continue;
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if (!MO.isDef())
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continue;
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// Get the first instruction that uses MO
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MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(MO.getReg());
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RI++;
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MachineInstr *UseMO = RI->getParent();
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unsigned LatencyOp = 0;
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if (UseMO && BlockTrace.isDepInTrace(Root, UseMO)) {
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LatencyOp = TSchedModel.computeOperandLatency(
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NewRoot, NewRoot->findRegisterDefOperandIdx(MO.getReg()), UseMO,
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UseMO->findRegisterUseOperandIdx(MO.getReg()));
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} else {
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LatencyOp = TSchedModel.computeInstrLatency(NewRoot->getOpcode());
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}
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NewRootLatency = std::max(NewRootLatency, LatencyOp);
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}
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return NewRootLatency;
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}
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/// preservesCriticalPathlen - True when the new instruction sequence does not
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/// lengthen the critical path. The DAGCombine code sequence ends in MI
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/// (Machine Instruction) Root. The new code sequence ends in MI NewRoot. A
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/// necessary condition for the new sequence to replace the old sequence is that
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/// is cannot lengthen the critical path. This is decided by the formula
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/// (NewRootDepth + NewRootLatency) <= (RootDepth + RootLatency + RootSlack)).
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/// The slack is the number of cycles Root can be delayed before the critical
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/// patch becomes longer.
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bool MachineCombiner::preservesCriticalPathLen(
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MachineBasicBlock *MBB, MachineInstr *Root,
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MachineTraceMetrics::Trace BlockTrace,
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SmallVectorImpl<MachineInstr *> &InsInstrs,
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DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) {
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assert(TSchedModel.hasInstrSchedModel() && "Missing machine model\n");
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// NewRoot is the last instruction in the \p InsInstrs vector
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// Get depth and latency of NewRoot
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unsigned NewRootIdx = InsInstrs.size() - 1;
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MachineInstr *NewRoot = InsInstrs[NewRootIdx];
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unsigned NewRootDepth = getDepth(InsInstrs, InstrIdxForVirtReg, BlockTrace);
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unsigned NewRootLatency = getLatency(Root, NewRoot, BlockTrace);
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// Get depth, latency and slack of Root
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unsigned RootDepth = BlockTrace.getInstrCycles(Root).Depth;
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unsigned RootLatency = TSchedModel.computeInstrLatency(Root);
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unsigned RootSlack = BlockTrace.getInstrSlack(Root);
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DEBUG(dbgs() << "DEPENDENCE DATA FOR " << Root << "\n";
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dbgs() << " NewRootDepth: " << NewRootDepth
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<< " NewRootLatency: " << NewRootLatency << "\n";
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dbgs() << " RootDepth: " << RootDepth << " RootLatency: " << RootLatency
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<< " RootSlack: " << RootSlack << "\n";
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dbgs() << " NewRootDepth + NewRootLatency "
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<< NewRootDepth + NewRootLatency << "\n";
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dbgs() << " RootDepth + RootLatency + RootSlack "
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<< RootDepth + RootLatency + RootSlack << "\n";);
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/// True when the new sequence does not lenghten the critical path.
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return ((NewRootDepth + NewRootLatency) <=
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(RootDepth + RootLatency + RootSlack));
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}
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/// helper routine to convert instructions into SC
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void MachineCombiner::instr2instrSC(
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SmallVectorImpl<MachineInstr *> &Instrs,
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SmallVectorImpl<const MCSchedClassDesc *> &InstrsSC) {
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for (auto *InstrPtr : Instrs) {
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unsigned Opc = InstrPtr->getOpcode();
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unsigned Idx = TII->get(Opc).getSchedClass();
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const MCSchedClassDesc *SC = SchedModel.getSchedClassDesc(Idx);
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InstrsSC.push_back(SC);
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}
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}
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/// preservesResourceLen - True when the new instructions do not increase
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/// resource length
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bool MachineCombiner::preservesResourceLen(
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MachineBasicBlock *MBB, MachineTraceMetrics::Trace BlockTrace,
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SmallVectorImpl<MachineInstr *> &InsInstrs,
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SmallVectorImpl<MachineInstr *> &DelInstrs) {
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// Compute current resource length
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//ArrayRef<const MachineBasicBlock *> MBBarr(MBB);
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SmallVector <const MachineBasicBlock *, 1> MBBarr;
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MBBarr.push_back(MBB);
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unsigned ResLenBeforeCombine = BlockTrace.getResourceLength(MBBarr);
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// Deal with SC rather than Instructions.
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SmallVector<const MCSchedClassDesc *, 16> InsInstrsSC;
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SmallVector<const MCSchedClassDesc *, 16> DelInstrsSC;
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instr2instrSC(InsInstrs, InsInstrsSC);
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instr2instrSC(DelInstrs, DelInstrsSC);
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ArrayRef<const MCSchedClassDesc *> MSCInsArr = makeArrayRef(InsInstrsSC);
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ArrayRef<const MCSchedClassDesc *> MSCDelArr = makeArrayRef(DelInstrsSC);
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// Compute new resource length
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unsigned ResLenAfterCombine =
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BlockTrace.getResourceLength(MBBarr, MSCInsArr, MSCDelArr);
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DEBUG(dbgs() << "RESOURCE DATA: \n";
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dbgs() << " resource len before: " << ResLenBeforeCombine
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<< " after: " << ResLenAfterCombine << "\n";);
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return ResLenAfterCombine <= ResLenBeforeCombine;
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}
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/// \returns true when new instruction sequence should be generated
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/// independent if it lenghtens critical path or not
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bool MachineCombiner::doSubstitute(unsigned NewSize, unsigned OldSize) {
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if (OptSize && (NewSize < OldSize))
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return true;
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if (!TSchedModel.hasInstrSchedModel())
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return true;
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return false;
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}
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/// combineInstructions - substitute a slow code sequence with a faster one by
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/// evaluating instruction combining pattern.
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/// The prototype of such a pattern is MUl + ADD -> MADD. Performs instruction
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/// combining based on machine trace metrics. Only combine a sequence of
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/// instructions when this neither lengthens the critical path nor increases
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/// resource pressure. When optimizing for codesize always combine when the new
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/// sequence is shorter.
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bool MachineCombiner::combineInstructions(MachineBasicBlock *MBB) {
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bool Changed = false;
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DEBUG(dbgs() << "Combining MBB " << MBB->getName() << "\n");
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auto BlockIter = MBB->begin();
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while (BlockIter != MBB->end()) {
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auto &MI = *BlockIter++;
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DEBUG(dbgs() << "INSTR "; MI.dump(); dbgs() << "\n";);
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SmallVector<MachineCombinerPattern::MC_PATTERN, 16> Pattern;
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// The motivating example is:
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//
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// MUL Other MUL_op1 MUL_op2 Other
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// \ / \ | /
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// ADD/SUB => MADD/MSUB
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// (=Root) (=NewRoot)
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// The DAGCombine code always replaced MUL + ADD/SUB by MADD. While this is
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// usually beneficial for code size it unfortunately can hurt performance
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// when the ADD is on the critical path, but the MUL is not. With the
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// substitution the MUL becomes part of the critical path (in form of the
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// MADD) and can lengthen it on architectures where the MADD latency is
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// longer than the ADD latency.
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//
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// For each instruction we check if it can be the root of a combiner
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// pattern. Then for each pattern the new code sequence in form of MI is
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// generated and evaluated. When the efficiency criteria (don't lengthen
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// critical path, don't use more resources) is met the new sequence gets
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// hooked up into the basic block before the old sequence is removed.
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//
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// The algorithm does not try to evaluate all patterns and pick the best.
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// This is only an artificial restriction though. In practice there is
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// mostly one pattern and hasPattern() can order patterns based on an
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// internal cost heuristic.
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if (TII->hasPattern(MI, Pattern)) {
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for (auto P : Pattern) {
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SmallVector<MachineInstr *, 16> InsInstrs;
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SmallVector<MachineInstr *, 16> DelInstrs;
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DenseMap<unsigned, unsigned> InstrIdxForVirtReg;
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if (!MinInstr)
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MinInstr = Traces->getEnsemble(MachineTraceMetrics::TS_MinInstrCount);
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MachineTraceMetrics::Trace BlockTrace = MinInstr->getTrace(MBB);
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Traces->verifyAnalysis();
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TII->genAlternativeCodeSequence(MI, P, InsInstrs, DelInstrs,
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InstrIdxForVirtReg);
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// Found pattern, but did not generate alternative sequence.
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// This can happen e.g. when an immediate could not be materialized
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// in a single instruction.
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if (!InsInstrs.size())
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continue;
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// Substitute when we optimize for codesize and the new sequence has
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// fewer instructions OR
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// the new sequence neither lenghten the critical path nor increases
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// resource pressure.
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if (doSubstitute(InsInstrs.size(), DelInstrs.size()) ||
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(preservesCriticalPathLen(MBB, &MI, BlockTrace, InsInstrs,
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InstrIdxForVirtReg) &&
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preservesResourceLen(MBB, BlockTrace, InsInstrs, DelInstrs))) {
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for (auto *InstrPtr : InsInstrs)
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MBB->insert((MachineBasicBlock::iterator) & MI,
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(MachineInstr *)InstrPtr);
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for (auto *InstrPtr : DelInstrs)
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InstrPtr->eraseFromParentAndMarkDBGValuesForRemoval();
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Changed = true;
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++NumInstCombined;
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Traces->invalidate(MBB);
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Traces->verifyAnalysis();
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// Eagerly stop after the first pattern fired
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break;
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} else {
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// Cleanup instructions of the alternative code sequence. There is no
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// use for them.
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for (auto *InstrPtr : InsInstrs) {
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MachineFunction *MF = MBB->getParent();
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MF->DeleteMachineInstr((MachineInstr *)InstrPtr);
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}
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}
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InstrIdxForVirtReg.clear();
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}
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}
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}
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return Changed;
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}
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bool MachineCombiner::runOnMachineFunction(MachineFunction &MF) {
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const TargetSubtargetInfo &STI =
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MF.getTarget().getSubtarget<TargetSubtargetInfo>();
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TII = STI.getInstrInfo();
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TRI = STI.getRegisterInfo();
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SchedModel = STI.getSchedModel();
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TSchedModel.init(SchedModel, &STI, TII);
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MRI = &MF.getRegInfo();
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Traces = &getAnalysis<MachineTraceMetrics>();
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MinInstr = 0;
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OptSize = MF.getFunction()->getAttributes().hasAttribute(
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AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
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DEBUG(dbgs() << getPassName() << ": " << MF.getName() << '\n');
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if (!TII->useMachineCombiner()) {
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DEBUG(dbgs() << " Skipping pass: Target does not support machine combiner\n");
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return false;
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}
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bool Changed = false;
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// Try to combine instructions.
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for (auto &MBB : MF)
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Changed |= combineInstructions(&MBB);
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return Changed;
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}
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