mirror of
https://github.com/c64scene-ar/llvm-6502.git
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2842c051b3
We were already always passing true, this just removes the option. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208205 91177308-0d34-0410-b5e6-96231b3b80d8
220 lines
8.9 KiB
C++
220 lines
8.9 KiB
C++
//===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides Mips specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#include "InstPrinter/MipsInstPrinter.h"
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#include "MipsELFStreamer.h"
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#include "MipsMCAsmInfo.h"
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#include "MipsMCNaCl.h"
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#include "MipsMCTargetDesc.h"
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#include "MipsTargetStreamer.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/MC/MCCodeGenInfo.h"
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#include "llvm/MC/MCELFStreamer.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/MC/MachineLocation.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define GET_INSTRINFO_MC_DESC
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#include "MipsGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "MipsGenSubtargetInfo.inc"
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#define GET_REGINFO_MC_DESC
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#include "MipsGenRegisterInfo.inc"
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/// Select the Mips CPU for the given triple and cpu name.
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/// FIXME: Merge with the copy in MipsSubtarget.cpp
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static inline StringRef selectMipsCPU(StringRef TT, StringRef CPU) {
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if (CPU.empty() || CPU == "generic") {
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Triple TheTriple(TT);
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if (TheTriple.getArch() == Triple::mips ||
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TheTriple.getArch() == Triple::mipsel)
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CPU = "mips32";
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else
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CPU = "mips64";
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}
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return CPU;
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}
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static MCInstrInfo *createMipsMCInstrInfo() {
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MCInstrInfo *X = new MCInstrInfo();
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InitMipsMCInstrInfo(X);
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return X;
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}
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static MCRegisterInfo *createMipsMCRegisterInfo(StringRef TT) {
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MCRegisterInfo *X = new MCRegisterInfo();
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InitMipsMCRegisterInfo(X, Mips::RA);
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return X;
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}
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static MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU,
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StringRef FS) {
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CPU = selectMipsCPU(TT, CPU);
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MCSubtargetInfo *X = new MCSubtargetInfo();
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InitMipsMCSubtargetInfo(X, TT, CPU, FS);
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return X;
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}
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static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
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MCAsmInfo *MAI = new MipsMCAsmInfo(TT);
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unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
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MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
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MAI->addInitialFrameState(Inst);
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return MAI;
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}
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static MCCodeGenInfo *createMipsMCCodeGenInfo(StringRef TT, Reloc::Model RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL) {
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MCCodeGenInfo *X = new MCCodeGenInfo();
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if (CM == CodeModel::JITDefault)
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RM = Reloc::Static;
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else if (RM == Reloc::Default)
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RM = Reloc::PIC_;
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X->InitMCCodeGenInfo(RM, CM, OL);
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return X;
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}
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static MCInstPrinter *createMipsMCInstPrinter(const Target &T,
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unsigned SyntaxVariant,
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const MCAsmInfo &MAI,
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const MCInstrInfo &MII,
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const MCRegisterInfo &MRI,
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const MCSubtargetInfo &STI) {
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return new MipsInstPrinter(MAI, MII, MRI);
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}
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static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
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MCContext &Context, MCAsmBackend &MAB,
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raw_ostream &OS, MCCodeEmitter *Emitter,
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const MCSubtargetInfo &STI,
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bool RelaxAll, bool NoExecStack) {
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MCStreamer *S;
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if (!Triple(TT).isOSNaCl())
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S = createMipsELFStreamer(Context, MAB, OS, Emitter, STI, RelaxAll,
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NoExecStack);
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else
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S = createMipsNaClELFStreamer(Context, MAB, OS, Emitter, STI, RelaxAll,
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NoExecStack);
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new MipsTargetELFStreamer(*S, STI);
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return S;
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}
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static MCStreamer *
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createMCAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS,
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bool isVerboseAsm, bool useDwarfDirectory,
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MCInstPrinter *InstPrint, MCCodeEmitter *CE,
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MCAsmBackend *TAB, bool ShowInst) {
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MCStreamer *S = llvm::createAsmStreamer(
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Ctx, OS, isVerboseAsm, useDwarfDirectory, InstPrint, CE, TAB, ShowInst);
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new MipsTargetAsmStreamer(*S, OS);
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return S;
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}
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extern "C" void LLVMInitializeMipsTargetMC() {
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// Register the MC asm info.
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RegisterMCAsmInfoFn X(TheMipsTarget, createMipsMCAsmInfo);
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RegisterMCAsmInfoFn Y(TheMipselTarget, createMipsMCAsmInfo);
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RegisterMCAsmInfoFn A(TheMips64Target, createMipsMCAsmInfo);
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RegisterMCAsmInfoFn B(TheMips64elTarget, createMipsMCAsmInfo);
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// Register the MC codegen info.
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TargetRegistry::RegisterMCCodeGenInfo(TheMipsTarget,
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createMipsMCCodeGenInfo);
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TargetRegistry::RegisterMCCodeGenInfo(TheMipselTarget,
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createMipsMCCodeGenInfo);
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TargetRegistry::RegisterMCCodeGenInfo(TheMips64Target,
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createMipsMCCodeGenInfo);
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TargetRegistry::RegisterMCCodeGenInfo(TheMips64elTarget,
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createMipsMCCodeGenInfo);
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// Register the MC instruction info.
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TargetRegistry::RegisterMCInstrInfo(TheMipsTarget, createMipsMCInstrInfo);
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TargetRegistry::RegisterMCInstrInfo(TheMipselTarget, createMipsMCInstrInfo);
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TargetRegistry::RegisterMCInstrInfo(TheMips64Target, createMipsMCInstrInfo);
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TargetRegistry::RegisterMCInstrInfo(TheMips64elTarget,
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createMipsMCInstrInfo);
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// Register the MC register info.
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TargetRegistry::RegisterMCRegInfo(TheMipsTarget, createMipsMCRegisterInfo);
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TargetRegistry::RegisterMCRegInfo(TheMipselTarget, createMipsMCRegisterInfo);
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TargetRegistry::RegisterMCRegInfo(TheMips64Target, createMipsMCRegisterInfo);
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TargetRegistry::RegisterMCRegInfo(TheMips64elTarget,
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createMipsMCRegisterInfo);
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// Register the MC Code Emitter
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TargetRegistry::RegisterMCCodeEmitter(TheMipsTarget,
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createMipsMCCodeEmitterEB);
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TargetRegistry::RegisterMCCodeEmitter(TheMipselTarget,
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createMipsMCCodeEmitterEL);
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TargetRegistry::RegisterMCCodeEmitter(TheMips64Target,
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createMipsMCCodeEmitterEB);
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TargetRegistry::RegisterMCCodeEmitter(TheMips64elTarget,
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createMipsMCCodeEmitterEL);
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// Register the object streamer.
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TargetRegistry::RegisterMCObjectStreamer(TheMipsTarget, createMCStreamer);
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TargetRegistry::RegisterMCObjectStreamer(TheMipselTarget, createMCStreamer);
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TargetRegistry::RegisterMCObjectStreamer(TheMips64Target, createMCStreamer);
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TargetRegistry::RegisterMCObjectStreamer(TheMips64elTarget,
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createMCStreamer);
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// Register the asm streamer.
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TargetRegistry::RegisterAsmStreamer(TheMipsTarget, createMCAsmStreamer);
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TargetRegistry::RegisterAsmStreamer(TheMipselTarget, createMCAsmStreamer);
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TargetRegistry::RegisterAsmStreamer(TheMips64Target, createMCAsmStreamer);
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TargetRegistry::RegisterAsmStreamer(TheMips64elTarget, createMCAsmStreamer);
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// Register the asm backend.
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TargetRegistry::RegisterMCAsmBackend(TheMipsTarget,
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createMipsAsmBackendEB32);
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TargetRegistry::RegisterMCAsmBackend(TheMipselTarget,
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createMipsAsmBackendEL32);
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TargetRegistry::RegisterMCAsmBackend(TheMips64Target,
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createMipsAsmBackendEB64);
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TargetRegistry::RegisterMCAsmBackend(TheMips64elTarget,
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createMipsAsmBackendEL64);
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// Register the MC subtarget info.
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TargetRegistry::RegisterMCSubtargetInfo(TheMipsTarget,
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createMipsMCSubtargetInfo);
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TargetRegistry::RegisterMCSubtargetInfo(TheMipselTarget,
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createMipsMCSubtargetInfo);
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TargetRegistry::RegisterMCSubtargetInfo(TheMips64Target,
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createMipsMCSubtargetInfo);
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TargetRegistry::RegisterMCSubtargetInfo(TheMips64elTarget,
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createMipsMCSubtargetInfo);
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// Register the MCInstPrinter.
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TargetRegistry::RegisterMCInstPrinter(TheMipsTarget,
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createMipsMCInstPrinter);
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TargetRegistry::RegisterMCInstPrinter(TheMipselTarget,
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createMipsMCInstPrinter);
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TargetRegistry::RegisterMCInstPrinter(TheMips64Target,
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createMipsMCInstPrinter);
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TargetRegistry::RegisterMCInstPrinter(TheMips64elTarget,
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createMipsMCInstPrinter);
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}
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