mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
e72fac60e3
but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Removal of redundant code and formatting fixes. Contributers: Jack Carter/Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172842 91177308-0d34-0410-b5e6-96231b3b80d8
359 lines
16 KiB
TableGen
359 lines
16 KiB
TableGen
//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Mips64 instructions.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Mips Operand, Complex Patterns and Transformations Definitions.
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//===----------------------------------------------------------------------===//
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// Instruction operand types
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def shamt_64 : Operand<i64>;
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// Unsigned Operand
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def uimm16_64 : Operand<i64> {
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let PrintMethod = "printUnsignedImm";
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}
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// Transformation Function - get Imm - 32.
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def Subtract32 : SDNodeXForm<imm, [{
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return getImm(N, (unsigned)N->getZExtValue() - 32);
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}]>;
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// shamt must fit in 6 bits.
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def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
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//===----------------------------------------------------------------------===//
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// Instructions specific format
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//===----------------------------------------------------------------------===//
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let DecoderNamespace = "Mips64" in {
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multiclass Atomic2Ops64<PatFrag Op> {
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def NAME : Atomic2Ops<Op, CPU64Regs, CPURegs>,
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Requires<[NotN64, HasStdEnc]>;
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def _P8 : Atomic2Ops<Op, CPU64Regs, CPU64Regs>,
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Requires<[IsN64, HasStdEnc]> {
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let isCodeGenOnly = 1;
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}
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}
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multiclass AtomicCmpSwap64<PatFrag Op> {
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def NAME : AtomicCmpSwap<Op, CPU64Regs, CPURegs>,
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Requires<[NotN64, HasStdEnc]>;
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def _P8 : AtomicCmpSwap<Op, CPU64Regs, CPU64Regs>,
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Requires<[IsN64, HasStdEnc]> {
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let isCodeGenOnly = 1;
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}
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}
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}
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let usesCustomInserter = 1, Predicates = [HasStdEnc],
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DecoderNamespace = "Mips64" in {
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defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64>;
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defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64>;
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defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64>;
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defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64>;
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defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64>;
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defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64>;
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defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64>;
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defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64>;
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}
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//===----------------------------------------------------------------------===//
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// Instruction definition
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//===----------------------------------------------------------------------===//
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let DecoderNamespace = "Mips64" in {
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/// Arithmetic Instructions (ALU Immediate)
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def DADDi : ArithLogicI<"daddi", simm16_64, CPU64RegsOpnd>, ADDI_FM<0x18>;
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def DADDiu : ArithLogicI<"daddiu", simm16_64, CPU64RegsOpnd, immSExt16, add>,
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ADDI_FM<0x19>, IsAsCheapAsAMove;
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def DANDi : ArithLogicI<"andi", uimm16_64, CPU64RegsOpnd, immZExt16, and>,
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ADDI_FM<0xc>;
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def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, CPU64Regs>,
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SLTI_FM<0xa>;
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def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, CPU64Regs>,
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SLTI_FM<0xb>;
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def ORi64 : ArithLogicI<"ori", uimm16_64, CPU64RegsOpnd, immZExt16, or>,
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ADDI_FM<0xd>;
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def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64RegsOpnd, immZExt16, xor>,
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ADDI_FM<0xe>;
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def LUi64 : LoadUpper<"lui", CPU64Regs, uimm16_64>, LUI_FM;
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/// Arithmetic Instructions (3-Operand, R-Type)
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def DADD : ArithLogicR<"dadd", CPU64RegsOpnd>, ADD_FM<0, 0x2c>;
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def DADDu : ArithLogicR<"daddu", CPU64RegsOpnd, 1, IIAlu, add>,
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ADD_FM<0, 0x2d>;
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def DSUBu : ArithLogicR<"dsubu", CPU64RegsOpnd, 0, IIAlu, sub>,
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ADD_FM<0, 0x2f>;
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def SLT64 : SetCC_R<"slt", setlt, CPU64Regs>, ADD_FM<0, 0x2a>;
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def SLTu64 : SetCC_R<"sltu", setult, CPU64Regs>, ADD_FM<0, 0x2b>;
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def AND64 : ArithLogicR<"and", CPU64RegsOpnd, 1, IIAlu, and>, ADD_FM<0, 0x24>;
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def OR64 : ArithLogicR<"or", CPU64RegsOpnd, 1, IIAlu, or>, ADD_FM<0, 0x25>;
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def XOR64 : ArithLogicR<"xor", CPU64RegsOpnd, 1, IIAlu, xor>, ADD_FM<0, 0x26>;
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def NOR64 : LogicNOR<"nor", CPU64RegsOpnd>, ADD_FM<0, 0x27>;
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/// Shift Instructions
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def DSLL : shift_rotate_imm<"dsll", shamt, CPU64RegsOpnd, shl, immZExt6>,
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SRA_FM<0x38, 0>;
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def DSRL : shift_rotate_imm<"dsrl", shamt, CPU64RegsOpnd, srl, immZExt6>,
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SRA_FM<0x3a, 0>;
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def DSRA : shift_rotate_imm<"dsra", shamt, CPU64RegsOpnd, sra, immZExt6>,
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SRA_FM<0x3b, 0>;
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def DSLLV : shift_rotate_reg<"dsllv", CPU64RegsOpnd, shl>, SRLV_FM<0x14, 0>;
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def DSRLV : shift_rotate_reg<"dsrlv", CPU64RegsOpnd, srl>, SRLV_FM<0x16, 0>;
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def DSRAV : shift_rotate_reg<"dsrav", CPU64RegsOpnd, sra>, SRLV_FM<0x17, 0>;
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def DSLL32 : shift_rotate_imm<"dsll32", shamt, CPU64RegsOpnd>, SRA_FM<0x3c, 0>;
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def DSRL32 : shift_rotate_imm<"dsrl32", shamt, CPU64RegsOpnd>, SRA_FM<0x3e, 0>;
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def DSRA32 : shift_rotate_imm<"dsra32", shamt, CPU64RegsOpnd>, SRA_FM<0x3f, 0>;
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}
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// Rotate Instructions
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let Predicates = [HasMips64r2, HasStdEnc],
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DecoderNamespace = "Mips64" in {
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def DROTR : shift_rotate_imm<"drotr", shamt, CPU64RegsOpnd, rotr, immZExt6>,
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SRA_FM<0x3a, 1>;
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def DROTRV : shift_rotate_reg<"drotrv", CPU64RegsOpnd, rotr>,
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SRLV_FM<0x16, 1>;
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}
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let DecoderNamespace = "Mips64" in {
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/// Load and Store Instructions
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/// aligned
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defm LB64 : LoadM<"lb", CPU64Regs, sextloadi8>, LW_FM<0x20>;
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defm LBu64 : LoadM<"lbu", CPU64Regs, zextloadi8>, LW_FM<0x24>;
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defm LH64 : LoadM<"lh", CPU64Regs, sextloadi16>, LW_FM<0x21>;
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defm LHu64 : LoadM<"lhu", CPU64Regs, zextloadi16>, LW_FM<0x25>;
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defm LW64 : LoadM<"lw", CPU64Regs, sextloadi32>, LW_FM<0x23>;
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defm LWu64 : LoadM<"lwu", CPU64Regs, zextloadi32>, LW_FM<0x27>;
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defm SB64 : StoreM<"sb", CPU64Regs, truncstorei8>, LW_FM<0x28>;
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defm SH64 : StoreM<"sh", CPU64Regs, truncstorei16>, LW_FM<0x29>;
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defm SW64 : StoreM<"sw", CPU64Regs, truncstorei32>, LW_FM<0x2b>;
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defm LD : LoadM<"ld", CPU64Regs, load>, LW_FM<0x37>;
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defm SD : StoreM<"sd", CPU64Regs, store>, LW_FM<0x3f>;
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/// load/store left/right
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defm LWL64 : LoadLeftRightM<"lwl", MipsLWL, CPU64Regs>, LW_FM<0x22>;
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defm LWR64 : LoadLeftRightM<"lwr", MipsLWR, CPU64Regs>, LW_FM<0x26>;
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defm SWL64 : StoreLeftRightM<"swl", MipsSWL, CPU64Regs>, LW_FM<0x2a>;
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defm SWR64 : StoreLeftRightM<"swr", MipsSWR, CPU64Regs>, LW_FM<0x2e>;
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defm LDL : LoadLeftRightM<"ldl", MipsLDL, CPU64Regs>, LW_FM<0x1a>;
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defm LDR : LoadLeftRightM<"ldr", MipsLDR, CPU64Regs>, LW_FM<0x1b>;
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defm SDL : StoreLeftRightM<"sdl", MipsSDL, CPU64Regs>, LW_FM<0x2c>;
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defm SDR : StoreLeftRightM<"sdr", MipsSDR, CPU64Regs>, LW_FM<0x2d>;
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/// Load-linked, Store-conditional
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let Predicates = [NotN64, HasStdEnc] in {
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def LLD : LLBase<"lld", CPU64RegsOpnd, mem>, LW_FM<0x34>;
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def SCD : SCBase<"scd", CPU64RegsOpnd, mem>, LW_FM<0x3c>;
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}
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let Predicates = [IsN64, HasStdEnc], isCodeGenOnly = 1 in {
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def LLD_P8 : LLBase<"lld", CPU64RegsOpnd, mem64>, LW_FM<0x34>;
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def SCD_P8 : SCBase<"scd", CPU64RegsOpnd, mem64>, LW_FM<0x3c>;
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}
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/// Jump and Branch Instructions
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def JR64 : IndirectBranch<CPU64Regs>, MTLO_FM<8>;
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def BEQ64 : CBranch<"beq", seteq, CPU64Regs>, BEQ_FM<4>;
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def BNE64 : CBranch<"bne", setne, CPU64Regs>, BEQ_FM<5>;
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def BGEZ64 : CBranchZero<"bgez", setge, CPU64Regs>, BGEZ_FM<1, 1>;
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def BGTZ64 : CBranchZero<"bgtz", setgt, CPU64Regs>, BGEZ_FM<7, 0>;
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def BLEZ64 : CBranchZero<"blez", setle, CPU64Regs>, BGEZ_FM<6, 0>;
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def BLTZ64 : CBranchZero<"bltz", setlt, CPU64Regs>, BGEZ_FM<1, 0>;
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}
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let DecoderNamespace = "Mips64" in
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def JALR64 : JumpLinkReg<"jalr", CPU64Regs>, JALR_FM;
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def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, MTLO_FM<8>, IsTailCall;
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let DecoderNamespace = "Mips64" in {
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/// Multiply and Divide Instructions.
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def DMULT : Mult<"dmult", IIImul, CPU64RegsOpnd, [HI64, LO64]>,
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MULT_FM<0, 0x1c>;
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def DMULTu : Mult<"dmultu", IIImul, CPU64RegsOpnd, [HI64, LO64]>,
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MULT_FM<0, 0x1d>;
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def DSDIV : Div<MipsDivRem, "ddiv", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>,
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MULT_FM<0, 0x1e>;
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def DUDIV : Div<MipsDivRemU, "ddivu", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>,
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MULT_FM<0, 0x1f>;
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def MTHI64 : MoveToLOHI<"mthi", CPU64Regs, [HI64]>, MTLO_FM<0x11>;
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def MTLO64 : MoveToLOHI<"mtlo", CPU64Regs, [LO64]>, MTLO_FM<0x13>;
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def MFHI64 : MoveFromLOHI<"mfhi", CPU64Regs, [HI64]>, MFLO_FM<0x10>;
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def MFLO64 : MoveFromLOHI<"mflo", CPU64Regs, [LO64]>, MFLO_FM<0x12>;
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/// Sign Ext In Register Instructions.
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def SEB64 : SignExtInReg<"seb", i8, CPU64Regs>, SEB_FM<0x10, 0x20>;
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def SEH64 : SignExtInReg<"seh", i16, CPU64Regs>, SEB_FM<0x18, 0x20>;
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/// Count Leading
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def DCLZ : CountLeading0<"dclz", CPU64RegsOpnd>, CLO_FM<0x24>;
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def DCLO : CountLeading1<"dclo", CPU64RegsOpnd>, CLO_FM<0x25>;
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/// Double Word Swap Bytes/HalfWords
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def DSBH : SubwordSwap<"dsbh", CPU64RegsOpnd>, SEB_FM<2, 0x24>;
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def DSHD : SubwordSwap<"dshd", CPU64RegsOpnd>, SEB_FM<5, 0x24>;
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def LEA_ADDiu64 : EffectiveAddress<"daddiu", CPU64Regs, mem_ea_64>, LW_FM<0x19>;
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}
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let DecoderNamespace = "Mips64" in {
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def RDHWR64 : ReadHardware<CPU64Regs, HW64RegsOpnd>, RDHWR_FM;
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def DEXT : ExtBase<"dext", CPU64RegsOpnd>, EXT_FM<3>;
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let Pattern = []<dag> in {
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def DEXTU : ExtBase<"dextu", CPU64RegsOpnd>, EXT_FM<2>;
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def DEXTM : ExtBase<"dextm", CPU64RegsOpnd>, EXT_FM<1>;
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}
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def DINS : InsBase<"dins", CPU64RegsOpnd>, EXT_FM<7>;
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let Pattern = []<dag> in {
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def DINSU : InsBase<"dinsu", CPU64RegsOpnd>, EXT_FM<6>;
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def DINSM : InsBase<"dinsm", CPU64RegsOpnd>, EXT_FM<5>;
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}
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let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
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def DSLL64_32 : FR<0x00, 0x3c, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
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"dsll\t$rd, $rt, 32", [], IIAlu>;
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def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
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"sll\t$rd, $rt, 0", [], IIAlu>;
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def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt),
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"sll\t$rd, $rt, 0", [], IIAlu>;
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}
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}
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//===----------------------------------------------------------------------===//
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// Arbitrary patterns that map to one or more instructions
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//===----------------------------------------------------------------------===//
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// extended loads
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let Predicates = [NotN64, HasStdEnc] in {
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def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
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def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
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def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
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def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
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}
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let Predicates = [IsN64, HasStdEnc] in {
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def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>;
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def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>;
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def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64_P8 addr:$src)>;
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def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64_P8 addr:$src)>;
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}
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// hi/lo relocs
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def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
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def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
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def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
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def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
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def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
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def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>;
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def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
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def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
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def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
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def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
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def : MipsPat<(MipsLo tglobaltlsaddr:$in),
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(DADDiu ZERO_64, tglobaltlsaddr:$in)>;
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def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>;
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def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)),
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(DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>;
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def : MipsPat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)),
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(DADDiu CPU64Regs:$hi, tblockaddress:$lo)>;
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def : MipsPat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)),
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(DADDiu CPU64Regs:$hi, tjumptable:$lo)>;
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def : MipsPat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)),
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(DADDiu CPU64Regs:$hi, tconstpool:$lo)>;
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def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)),
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(DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>;
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def : WrapperPat<tglobaladdr, DADDiu, CPU64Regs>;
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def : WrapperPat<tconstpool, DADDiu, CPU64Regs>;
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def : WrapperPat<texternalsym, DADDiu, CPU64Regs>;
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def : WrapperPat<tblockaddress, DADDiu, CPU64Regs>;
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def : WrapperPat<tjumptable, DADDiu, CPU64Regs>;
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def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>;
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defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
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ZERO_64>;
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// setcc patterns
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defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>;
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defm : SetlePats<CPU64Regs, SLT64, SLTu64>;
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defm : SetgtPats<CPU64Regs, SLT64, SLTu64>;
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defm : SetgePats<CPU64Regs, SLT64, SLTu64>;
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defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>;
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// truncate
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def : MipsPat<(i32 (trunc CPU64Regs:$src)),
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(SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>,
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Requires<[IsN64, HasStdEnc]>;
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// 32-to-64-bit extension
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def : MipsPat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
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def : MipsPat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>;
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def : MipsPat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
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// Sign extend in register
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def : MipsPat<(i64 (sext_inreg CPU64Regs:$src, i32)),
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(SLL64_64 CPU64Regs:$src)>;
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// bswap MipsPattern
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def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>;
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//===----------------------------------------------------------------------===//
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// Instruction aliases
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//===----------------------------------------------------------------------===//
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def : InstAlias<"move $dst, $src", (DADDu CPU64RegsOpnd:$dst,
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CPU64RegsOpnd:$src,ZERO_64)>,
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Requires<[HasMips64]>;
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def : InstAlias<"and $rs, $rt, $imm",
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(DANDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm)>,
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Requires<[HasMips64]>;
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def : InstAlias<"slt $rs, $rt, $imm",
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(SLTi64 CPURegsOpnd:$rs, CPU64Regs:$rt, simm16_64:$imm)>,
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Requires<[HasMips64]>;
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def : InstAlias<"xor $rs, $rt, $imm",
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(XORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm)>,
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Requires<[HasMips64]>;
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def : InstAlias<"not $rt, $rs",
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(NOR64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rs, ZERO_64)>,
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Requires<[HasMips64]>;
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def : InstAlias<"j $rs", (JR64 CPU64Regs:$rs)>, Requires<[HasMips64]>;
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def : InstAlias<"daddu $rs, $rt, $imm",
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(DADDiu CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm)>;
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def : InstAlias<"dadd $rs, $rt, $imm",
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(DADDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm)>;
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/// Move between CPU and coprocessor registers
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let DecoderNamespace = "Mips64" in {
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def DMFC0_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rt),
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(ins CPU64RegsOpnd:$rd, uimm16:$sel),
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"dmfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 1>;
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def DMTC0_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rd, uimm16:$sel),
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(ins CPU64RegsOpnd:$rt),
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"dmtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 5>;
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def DMFC2_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rt),
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(ins CPU64RegsOpnd:$rd, uimm16:$sel),
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"dmfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 1>;
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def DMTC2_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rd, uimm16:$sel),
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(ins CPU64RegsOpnd:$rt),
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"dmtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 5>;
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}
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// Two operand (implicit 0 selector) versions:
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def : InstAlias<"dmfc0 $rt, $rd",
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(DMFC0_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0)>;
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def : InstAlias<"dmtc0 $rt, $rd",
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(DMTC0_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt)>;
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def : InstAlias<"dmfc2 $rt, $rd",
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(DMFC2_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0)>;
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def : InstAlias<"dmtc2 $rt, $rd",
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(DMTC2_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt)>;
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