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https://github.com/c64scene-ar/llvm-6502.git
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352aa503fa
On Nehalem and newer CPUs there is a 2 cycle latency penalty on using a register in a different domain than where it was defined. Some instructions have equvivalents for different domains, like por/orps/orpd. The SSEDomainFix pass tries to minimize the number of domain crossings by changing between equvivalent opcodes where possible. This is a work in progress, in particular the pass doesn't do anything yet. SSE instructions are tagged with their execution domain in TableGen using the last two bits of TSFlags. Note that not all instructions are tagged correctly. Life just isn't that simple. The SSE execution domain issue is very similar to the ARM NEON/VFP pipeline issue handled by NEONMoveFixPass. This pass may become target independent to handle both. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99524 91177308-0d34-0410-b5e6-96231b3b80d8
93 lines
3.2 KiB
C++
93 lines
3.2 KiB
C++
//===-- X86TargetMachine.h - Define TargetMachine for the X86 ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the X86 specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86TARGETMACHINE_H
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#define X86TARGETMACHINE_H
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "X86.h"
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#include "X86ELFWriterInfo.h"
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#include "X86InstrInfo.h"
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#include "X86JITInfo.h"
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#include "X86Subtarget.h"
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#include "X86ISelLowering.h"
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namespace llvm {
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class formatted_raw_ostream;
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class X86TargetMachine : public LLVMTargetMachine {
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X86Subtarget Subtarget;
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const TargetData DataLayout; // Calculates type size & alignment
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TargetFrameInfo FrameInfo;
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X86InstrInfo InstrInfo;
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X86JITInfo JITInfo;
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X86TargetLowering TLInfo;
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X86ELFWriterInfo ELFWriterInfo;
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Reloc::Model DefRelocModel; // Reloc model before it's overridden.
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private:
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// We have specific defaults for X86.
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virtual void setCodeModelForJIT();
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virtual void setCodeModelForStatic();
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public:
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X86TargetMachine(const Target &T, const std::string &TT,
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const std::string &FS, bool is64Bit);
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virtual const X86InstrInfo *getInstrInfo() const { return &InstrInfo; }
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virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; }
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virtual X86JITInfo *getJITInfo() { return &JITInfo; }
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virtual const X86Subtarget *getSubtargetImpl() const{ return &Subtarget; }
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virtual X86TargetLowering *getTargetLowering() const {
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return const_cast<X86TargetLowering*>(&TLInfo);
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}
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virtual const X86RegisterInfo *getRegisterInfo() const {
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return &InstrInfo.getRegisterInfo();
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}
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virtual const TargetData *getTargetData() const { return &DataLayout; }
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virtual const X86ELFWriterInfo *getELFWriterInfo() const {
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return Subtarget.isTargetELF() ? &ELFWriterInfo : 0;
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}
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// Set up the pass pipeline.
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virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
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virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
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virtual bool addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
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virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
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virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
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JITCodeEmitter &JCE);
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};
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/// X86_32TargetMachine - X86 32-bit target machine.
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///
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class X86_32TargetMachine : public X86TargetMachine {
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public:
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X86_32TargetMachine(const Target &T, const std::string &M,
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const std::string &FS);
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};
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/// X86_64TargetMachine - X86 64-bit target machine.
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///
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class X86_64TargetMachine : public X86TargetMachine {
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public:
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X86_64TargetMachine(const Target &T, const std::string &TT,
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const std::string &FS);
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};
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} // End llvm namespace
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#endif
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