Kit Barton f60b0de42a This change implements the following three logical vector operations: ...

veqv (vector equivalence)
vnand
vorc
I increased the AddedComplexity for these instructions to 500 to ensure they are generated instead of issuing other VSX instructions.


Phabricator review: http://reviews.llvm.org/D7469


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228580 91177308-0d34-0410-b5e6-96231b3b80d8

2015-02-09 17:03:18 +00:00

..

AArch64

Fix some unnoticed/unwanted behavior change from r222319.

2015-02-04 03:10:03 +00:00

ARM

[ARM] Fix subtarget feature set truncation when using .cpu directive

2015-02-04 16:23:24 +00:00

AsmParser

MC: Don't emit .no_dead_strip on targets which don't support it

2014-12-24 04:11:42 +00:00

COFF

MC: Calculate intra-section symbol differences correctly for COFF

2015-02-09 06:31:31 +00:00

Disassembler

This change implements the following three logical vector operations:

2015-02-09 17:03:18 +00:00

ELF

Revert llvm/test/MC/ELF/noexec.s in r227074, "Fix a problem where the AArch64 ELF assembler was failing with"

2015-01-26 09:30:29 +00:00

Hexagon

[Hexagon] Updating predicate register transfers and adding tstbit to allow select selection. Updating ll tests with predicate transfers that previously had nop encodings.

2014-12-09 18:16:49 +00:00

MachO

Add r224985 back with fixes.

2015-01-19 21:11:14 +00:00

Markup

…

Mips

[mips] Fix FileCheck prefixes with whitespace between 'CHECK' and ':'

2015-02-06 16:37:30 +00:00

PowerPC

This change implements the following three logical vector operations:

2015-02-09 17:03:18 +00:00

R600

R600/SI: Add a stub GCNTargetMachine

2015-01-06 18:00:21 +00:00

Sparc

…

SystemZ

…

X86

[X86] Add GETSEC instruction.

2015-02-07 23:36:36 +00:00