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https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
64 lines
2.1 KiB
LLVM
64 lines
2.1 KiB
LLVM
; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s -mcpu=cyclone | FileCheck %s
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define <8 x i16> @testShiftRightArith_v8i16(<8 x i16> %a, <8 x i16> %b) #0 {
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; CHECK-LABEL: testShiftRightArith_v8i16:
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; CHECK: neg.8h [[REG1:v[0-9]+]], [[REG1]]
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; CHECK-NEXT: sshl.8h [[REG2:v[0-9]+]], [[REG2]], [[REG1]]
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entry:
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%a.addr = alloca <8 x i16>, align 16
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%b.addr = alloca <8 x i16>, align 16
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store <8 x i16> %a, <8 x i16>* %a.addr, align 16
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store <8 x i16> %b, <8 x i16>* %b.addr, align 16
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%0 = load <8 x i16>, <8 x i16>* %a.addr, align 16
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%1 = load <8 x i16>, <8 x i16>* %b.addr, align 16
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%shr = ashr <8 x i16> %0, %1
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ret <8 x i16> %shr
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}
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define <4 x i32> @testShiftRightArith_v4i32(<4 x i32> %a, <4 x i32> %b) #0 {
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; CHECK-LABEL: testShiftRightArith_v4i32:
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; CHECK: neg.4s [[REG3:v[0-9]+]], [[REG3]]
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; CHECK-NEXT: sshl.4s [[REG4:v[0-9]+]], [[REG4]], [[REG3]]
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entry:
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%a.addr = alloca <4 x i32>, align 32
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%b.addr = alloca <4 x i32>, align 32
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store <4 x i32> %a, <4 x i32>* %a.addr, align 32
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store <4 x i32> %b, <4 x i32>* %b.addr, align 32
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%0 = load <4 x i32>, <4 x i32>* %a.addr, align 32
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%1 = load <4 x i32>, <4 x i32>* %b.addr, align 32
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%shr = ashr <4 x i32> %0, %1
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ret <4 x i32> %shr
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}
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define <8 x i16> @testShiftRightLogical(<8 x i16> %a, <8 x i16> %b) #0 {
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; CHECK: testShiftRightLogical
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; CHECK: neg.8h [[REG5:v[0-9]+]], [[REG5]]
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; CHECK-NEXT: ushl.8h [[REG6:v[0-9]+]], [[REG6]], [[REG5]]
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entry:
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%a.addr = alloca <8 x i16>, align 16
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%b.addr = alloca <8 x i16>, align 16
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store <8 x i16> %a, <8 x i16>* %a.addr, align 16
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store <8 x i16> %b, <8 x i16>* %b.addr, align 16
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%0 = load <8 x i16>, <8 x i16>* %a.addr, align 16
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%1 = load <8 x i16>, <8 x i16>* %b.addr, align 16
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%shr = lshr <8 x i16> %0, %1
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ret <8 x i16> %shr
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}
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define <1 x i64> @sshr_v1i64(<1 x i64> %A) nounwind {
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; CHECK-LABEL: sshr_v1i64:
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; CHECK: sshr d0, d0, #63
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%tmp3 = ashr <1 x i64> %A, < i64 63 >
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ret <1 x i64> %tmp3
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}
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define <1 x i64> @ushr_v1i64(<1 x i64> %A) nounwind {
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; CHECK-LABEL: ushr_v1i64:
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; CHECK: ushr d0, d0, #63
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%tmp3 = lshr <1 x i64> %A, < i64 63 >
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ret <1 x i64> %tmp3
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}
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attributes #0 = { nounwind }
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