Tom Stellard f799b25cfc AMDGPU/SI: Add VI patterns to select FLAT instructions for global memory ops ... Summary: The MUBUF addr64 bit has been removed on VI, so we must use FLAT instructions when the pointer is stored in VGPRs. Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11067 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242673 91177308-0d34-0410-b5e6-96231b3b80d8		2015-07-20 14:28:41 +00:00
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AArch64	[RAGreedy] Add an experimental deferred spilling feature.	2015-07-17 23:04:06 +00:00
AMDGPU	AMDGPU/SI: Add VI patterns to select FLAT instructions for global memory ops	2015-07-20 14:28:41 +00:00
ARM	ARM: Enable MachineScheduler and disable PostRAScheduler for swift.	2015-07-17 23:18:30 +00:00
BPF
CPP
Generic
Hexagon	[Hexagon] Generate instructions for operations on predicate registers	2015-07-14 19:30:21 +00:00
Inputs
Mips	[SDAG] Optimize unordered comparison in soft-float mode (patch by Anton Nadolskiy)	2015-07-15 08:39:35 +00:00
MIR	MIR Parser: Allow the dollar characters in all of the identifier tokens.	2015-07-17 22:48:04 +00:00
MSP430
NVPTX	Use inbounds GEPs for memcpy and memset lowering	2015-07-17 16:42:33 +00:00
PowerPC	[PowerPC] v4i32 is a VSRCRegClass	2015-07-16 21:14:07 +00:00
SPARC	[SPARC] Cleanup handling of the Y/ASR registers.	2015-07-08 16:25:12 +00:00
SystemZ
Thumb
Thumb2	ARM: Add scheduling information for LDRLIT instructions to swift scheduling model	2015-07-17 23:18:26 +00:00
WebAssembly
WinEH	[WinEH] Strip the \01 character from the __CxxFrameHandler3 thunk name	2015-07-13 17:55:14 +00:00
X86	[X86][SSE] Tidied up vector CTLZ/CTTZ. NFCI.	2015-07-19 17:09:43 +00:00
XCore