mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-16 11:30:51 +00:00
a39058aaed
Also removes some redundant DNI comments on function declarations already using the macro. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175466 91177308-0d34-0410-b5e6-96231b3b80d8
582 lines
16 KiB
C++
582 lines
16 KiB
C++
//===- R600MCCodeEmitter.cpp - Code Emitter for R600->Cayman GPU families -===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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///
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/// This code emitter outputs bytecode that is understood by the r600g driver
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/// in the Mesa [1] project. The bytecode is very similar to the hardware's ISA,
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/// but it still needs to be run through a finalizer in order to be executed
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/// by the GPU.
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///
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/// [1] http://www.mesa3d.org/
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//
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//===----------------------------------------------------------------------===//
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#include "R600Defines.h"
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#include "MCTargetDesc/AMDGPUMCCodeEmitter.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/raw_ostream.h"
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#include <stdio.h>
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#define SRC_BYTE_COUNT 11
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#define DST_BYTE_COUNT 5
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using namespace llvm;
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namespace {
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class R600MCCodeEmitter : public AMDGPUMCCodeEmitter {
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R600MCCodeEmitter(const R600MCCodeEmitter &) LLVM_DELETED_FUNCTION;
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void operator=(const R600MCCodeEmitter &) LLVM_DELETED_FUNCTION;
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const MCInstrInfo &MCII;
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const MCRegisterInfo &MRI;
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const MCSubtargetInfo &STI;
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MCContext &Ctx;
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public:
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R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
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const MCSubtargetInfo &sti, MCContext &ctx)
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: MCII(mcii), MRI(mri), STI(sti), Ctx(ctx) { }
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/// \brief Encode the instruction and write it to the OS.
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virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// \returns the encoding for an MCOperand.
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virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups) const;
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private:
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void EmitALUInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
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raw_ostream &OS) const;
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void EmitSrc(const MCInst &MI, unsigned OpIdx, raw_ostream &OS) const;
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void EmitSrcISA(const MCInst &MI, unsigned RegOpIdx, unsigned SelOpIdx,
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raw_ostream &OS) const;
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void EmitDst(const MCInst &MI, raw_ostream &OS) const;
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void EmitTexInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
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raw_ostream &OS) const;
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void EmitFCInstr(const MCInst &MI, raw_ostream &OS) const;
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void EmitNullBytes(unsigned int byteCount, raw_ostream &OS) const;
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void EmitByte(unsigned int byte, raw_ostream &OS) const;
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void EmitTwoBytes(uint32_t bytes, raw_ostream &OS) const;
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void Emit(uint32_t value, raw_ostream &OS) const;
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void Emit(uint64_t value, raw_ostream &OS) const;
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unsigned getHWRegChan(unsigned reg) const;
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unsigned getHWReg(unsigned regNo) const;
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bool isFCOp(unsigned opcode) const;
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bool isTexOp(unsigned opcode) const;
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bool isFlagSet(const MCInst &MI, unsigned Operand, unsigned Flag) const;
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};
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} // End anonymous namespace
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enum RegElement {
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ELEMENT_X = 0,
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ELEMENT_Y,
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ELEMENT_Z,
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ELEMENT_W
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};
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enum InstrTypes {
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INSTR_ALU = 0,
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INSTR_TEX,
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INSTR_FC,
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INSTR_NATIVE,
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INSTR_VTX,
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INSTR_EXPORT
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};
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enum FCInstr {
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FC_IF_PREDICATE = 0,
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FC_ELSE,
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FC_ENDIF,
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FC_BGNLOOP,
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FC_ENDLOOP,
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FC_BREAK_PREDICATE,
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FC_CONTINUE
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};
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enum TextureTypes {
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TEXTURE_1D = 1,
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TEXTURE_2D,
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TEXTURE_3D,
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TEXTURE_CUBE,
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TEXTURE_RECT,
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TEXTURE_SHADOW1D,
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TEXTURE_SHADOW2D,
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TEXTURE_SHADOWRECT,
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TEXTURE_1D_ARRAY,
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TEXTURE_2D_ARRAY,
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TEXTURE_SHADOW1D_ARRAY,
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TEXTURE_SHADOW2D_ARRAY
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};
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MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new R600MCCodeEmitter(MCII, MRI, STI, Ctx);
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}
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void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const {
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if (isTexOp(MI.getOpcode())) {
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EmitTexInstr(MI, Fixups, OS);
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} else if (isFCOp(MI.getOpcode())){
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EmitFCInstr(MI, OS);
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} else if (MI.getOpcode() == AMDGPU::RETURN ||
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MI.getOpcode() == AMDGPU::BUNDLE ||
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MI.getOpcode() == AMDGPU::KILL) {
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return;
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} else {
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switch(MI.getOpcode()) {
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case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
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case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
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uint64_t inst = getBinaryCodeForInstr(MI, Fixups);
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EmitByte(INSTR_NATIVE, OS);
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Emit(inst, OS);
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break;
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}
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case AMDGPU::CONSTANT_LOAD_eg:
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case AMDGPU::VTX_READ_PARAM_8_eg:
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case AMDGPU::VTX_READ_PARAM_16_eg:
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case AMDGPU::VTX_READ_PARAM_32_eg:
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case AMDGPU::VTX_READ_PARAM_128_eg:
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case AMDGPU::VTX_READ_GLOBAL_8_eg:
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case AMDGPU::VTX_READ_GLOBAL_32_eg:
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case AMDGPU::VTX_READ_GLOBAL_128_eg:
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case AMDGPU::TEX_VTX_CONSTBUF:
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case AMDGPU::TEX_VTX_TEXBUF : {
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uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups);
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uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset
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EmitByte(INSTR_VTX, OS);
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Emit(InstWord01, OS);
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Emit(InstWord2, OS);
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break;
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}
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case AMDGPU::EG_ExportSwz:
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case AMDGPU::R600_ExportSwz:
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case AMDGPU::EG_ExportBuf:
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case AMDGPU::R600_ExportBuf: {
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uint64_t Inst = getBinaryCodeForInstr(MI, Fixups);
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EmitByte(INSTR_EXPORT, OS);
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Emit(Inst, OS);
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break;
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}
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default:
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EmitALUInstr(MI, Fixups, OS);
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break;
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}
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}
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}
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void R600MCCodeEmitter::EmitALUInstr(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixups,
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raw_ostream &OS) const {
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const MCInstrDesc &MCDesc = MCII.get(MI.getOpcode());
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// Emit instruction type
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EmitByte(INSTR_ALU, OS);
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uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups);
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//older alu have different encoding for instructions with one or two src
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//parameters.
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if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) &&
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!(MCDesc.TSFlags & R600_InstFlag::OP3)) {
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uint64_t ISAOpCode = InstWord01 & (0x3FFULL << 39);
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InstWord01 &= ~(0x3FFULL << 39);
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InstWord01 |= ISAOpCode << 1;
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}
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unsigned SrcNum = MCDesc.TSFlags & R600_InstFlag::OP3 ? 3 :
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MCDesc.TSFlags & R600_InstFlag::OP2 ? 2 : 1;
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EmitByte(SrcNum, OS);
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const unsigned SrcOps[3][2] = {
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{R600Operands::SRC0, R600Operands::SRC0_SEL},
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{R600Operands::SRC1, R600Operands::SRC1_SEL},
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{R600Operands::SRC2, R600Operands::SRC2_SEL}
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};
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for (unsigned SrcIdx = 0; SrcIdx < SrcNum; ++SrcIdx) {
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unsigned RegOpIdx = R600Operands::ALUOpTable[SrcNum-1][SrcOps[SrcIdx][0]];
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unsigned SelOpIdx = R600Operands::ALUOpTable[SrcNum-1][SrcOps[SrcIdx][1]];
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EmitSrcISA(MI, RegOpIdx, SelOpIdx, OS);
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}
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Emit(InstWord01, OS);
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return;
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}
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void R600MCCodeEmitter::EmitSrc(const MCInst &MI, unsigned OpIdx,
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raw_ostream &OS) const {
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const MCOperand &MO = MI.getOperand(OpIdx);
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union {
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float f;
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uint32_t i;
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} Value;
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Value.i = 0;
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// Emit the source select (2 bytes). For GPRs, this is the register index.
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// For other potential instruction operands, (e.g. constant registers) the
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// value of the source select is defined in the r600isa docs.
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if (MO.isReg()) {
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unsigned reg = MO.getReg();
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EmitTwoBytes(getHWReg(reg), OS);
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if (reg == AMDGPU::ALU_LITERAL_X) {
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unsigned ImmOpIndex = MI.getNumOperands() - 1;
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MCOperand ImmOp = MI.getOperand(ImmOpIndex);
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if (ImmOp.isFPImm()) {
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Value.f = ImmOp.getFPImm();
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} else {
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assert(ImmOp.isImm());
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Value.i = ImmOp.getImm();
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}
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}
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} else {
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// XXX: Handle other operand types.
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EmitTwoBytes(0, OS);
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}
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// Emit the source channel (1 byte)
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if (MO.isReg()) {
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EmitByte(getHWRegChan(MO.getReg()), OS);
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} else {
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EmitByte(0, OS);
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}
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// XXX: Emit isNegated (1 byte)
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if ((!(isFlagSet(MI, OpIdx, MO_FLAG_ABS)))
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&& (isFlagSet(MI, OpIdx, MO_FLAG_NEG) ||
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(MO.isReg() &&
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(MO.getReg() == AMDGPU::NEG_ONE || MO.getReg() == AMDGPU::NEG_HALF)))){
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EmitByte(1, OS);
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} else {
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EmitByte(0, OS);
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}
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// Emit isAbsolute (1 byte)
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if (isFlagSet(MI, OpIdx, MO_FLAG_ABS)) {
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EmitByte(1, OS);
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} else {
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EmitByte(0, OS);
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}
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// XXX: Emit relative addressing mode (1 byte)
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EmitByte(0, OS);
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// Emit kc_bank, This will be adjusted later by r600_asm
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EmitByte(0, OS);
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// Emit the literal value, if applicable (4 bytes).
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Emit(Value.i, OS);
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}
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void R600MCCodeEmitter::EmitSrcISA(const MCInst &MI, unsigned RegOpIdx,
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unsigned SelOpIdx, raw_ostream &OS) const {
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const MCOperand &RegMO = MI.getOperand(RegOpIdx);
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const MCOperand &SelMO = MI.getOperand(SelOpIdx);
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union {
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float f;
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uint32_t i;
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} InlineConstant;
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InlineConstant.i = 0;
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// Emit source type (1 byte) and source select (4 bytes). For GPRs type is 0
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// and select is 0 (GPR index is encoded in the instr encoding. For constants
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// type is 1 and select is the original const select passed from the driver.
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unsigned Reg = RegMO.getReg();
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if (Reg == AMDGPU::ALU_CONST) {
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EmitByte(1, OS);
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uint32_t Sel = SelMO.getImm();
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Emit(Sel, OS);
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} else {
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EmitByte(0, OS);
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Emit((uint32_t)0, OS);
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}
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if (Reg == AMDGPU::ALU_LITERAL_X) {
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unsigned ImmOpIndex = MI.getNumOperands() - 1;
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MCOperand ImmOp = MI.getOperand(ImmOpIndex);
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if (ImmOp.isFPImm()) {
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InlineConstant.f = ImmOp.getFPImm();
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} else {
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assert(ImmOp.isImm());
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InlineConstant.i = ImmOp.getImm();
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}
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}
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// Emit the literal value, if applicable (4 bytes).
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Emit(InlineConstant.i, OS);
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}
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void R600MCCodeEmitter::EmitTexInstr(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixups,
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raw_ostream &OS) const {
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unsigned Opcode = MI.getOpcode();
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bool hasOffsets = (Opcode == AMDGPU::TEX_LD);
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unsigned OpOffset = hasOffsets ? 3 : 0;
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int64_t Resource = MI.getOperand(OpOffset + 2).getImm();
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int64_t Sampler = MI.getOperand(OpOffset + 3).getImm();
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int64_t TextureType = MI.getOperand(OpOffset + 4).getImm();
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unsigned srcSelect[4] = {0, 1, 2, 3};
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// Emit instruction type
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EmitByte(1, OS);
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// Emit instruction
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EmitByte(getBinaryCodeForInstr(MI, Fixups), OS);
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// Emit resource id
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EmitByte(Resource, OS);
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// Emit source register
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EmitByte(getHWReg(MI.getOperand(1).getReg()), OS);
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// XXX: Emit src isRelativeAddress
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EmitByte(0, OS);
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// Emit destination register
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EmitByte(getHWReg(MI.getOperand(0).getReg()), OS);
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// XXX: Emit dst isRealtiveAddress
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EmitByte(0, OS);
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// XXX: Emit dst select
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EmitByte(0, OS); // X
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EmitByte(1, OS); // Y
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EmitByte(2, OS); // Z
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EmitByte(3, OS); // W
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// XXX: Emit lod bias
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EmitByte(0, OS);
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// XXX: Emit coord types
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unsigned coordType[4] = {1, 1, 1, 1};
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if (TextureType == TEXTURE_RECT
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|| TextureType == TEXTURE_SHADOWRECT) {
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coordType[ELEMENT_X] = 0;
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coordType[ELEMENT_Y] = 0;
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}
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if (TextureType == TEXTURE_1D_ARRAY
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|| TextureType == TEXTURE_SHADOW1D_ARRAY) {
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if (Opcode == AMDGPU::TEX_SAMPLE_C_L || Opcode == AMDGPU::TEX_SAMPLE_C_LB) {
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coordType[ELEMENT_Y] = 0;
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} else {
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coordType[ELEMENT_Z] = 0;
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srcSelect[ELEMENT_Z] = ELEMENT_Y;
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}
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} else if (TextureType == TEXTURE_2D_ARRAY
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|| TextureType == TEXTURE_SHADOW2D_ARRAY) {
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coordType[ELEMENT_Z] = 0;
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}
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for (unsigned i = 0; i < 4; i++) {
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EmitByte(coordType[i], OS);
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}
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// XXX: Emit offsets
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if (hasOffsets)
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for (unsigned i = 2; i < 5; i++)
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EmitByte(MI.getOperand(i).getImm()<<1, OS);
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else
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EmitNullBytes(3, OS);
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// Emit sampler id
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EmitByte(Sampler, OS);
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// XXX:Emit source select
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if ((TextureType == TEXTURE_SHADOW1D
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|| TextureType == TEXTURE_SHADOW2D
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|| TextureType == TEXTURE_SHADOWRECT
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|| TextureType == TEXTURE_SHADOW1D_ARRAY)
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&& Opcode != AMDGPU::TEX_SAMPLE_C_L
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&& Opcode != AMDGPU::TEX_SAMPLE_C_LB) {
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srcSelect[ELEMENT_W] = ELEMENT_Z;
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}
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for (unsigned i = 0; i < 4; i++) {
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EmitByte(srcSelect[i], OS);
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}
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}
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void R600MCCodeEmitter::EmitFCInstr(const MCInst &MI, raw_ostream &OS) const {
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// Emit instruction type
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EmitByte(INSTR_FC, OS);
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// Emit SRC
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unsigned NumOperands = MI.getNumOperands();
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if (NumOperands > 0) {
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assert(NumOperands == 1);
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EmitSrc(MI, 0, OS);
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} else {
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EmitNullBytes(SRC_BYTE_COUNT, OS);
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}
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// Emit FC Instruction
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enum FCInstr instr;
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switch (MI.getOpcode()) {
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case AMDGPU::PREDICATED_BREAK:
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instr = FC_BREAK_PREDICATE;
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break;
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case AMDGPU::CONTINUE:
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instr = FC_CONTINUE;
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break;
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case AMDGPU::IF_PREDICATE_SET:
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instr = FC_IF_PREDICATE;
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break;
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case AMDGPU::ELSE:
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instr = FC_ELSE;
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break;
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case AMDGPU::ENDIF:
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instr = FC_ENDIF;
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break;
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case AMDGPU::ENDLOOP:
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instr = FC_ENDLOOP;
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break;
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case AMDGPU::WHILELOOP:
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instr = FC_BGNLOOP;
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break;
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default:
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abort();
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break;
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}
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EmitByte(instr, OS);
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}
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void R600MCCodeEmitter::EmitNullBytes(unsigned int ByteCount,
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raw_ostream &OS) const {
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for (unsigned int i = 0; i < ByteCount; i++) {
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EmitByte(0, OS);
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}
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}
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void R600MCCodeEmitter::EmitByte(unsigned int Byte, raw_ostream &OS) const {
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OS.write((uint8_t) Byte & 0xff);
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}
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void R600MCCodeEmitter::EmitTwoBytes(unsigned int Bytes,
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raw_ostream &OS) const {
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OS.write((uint8_t) (Bytes & 0xff));
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OS.write((uint8_t) ((Bytes >> 8) & 0xff));
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}
|
|
|
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void R600MCCodeEmitter::Emit(uint32_t Value, raw_ostream &OS) const {
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|
for (unsigned i = 0; i < 4; i++) {
|
|
OS.write((uint8_t) ((Value >> (8 * i)) & 0xff));
|
|
}
|
|
}
|
|
|
|
void R600MCCodeEmitter::Emit(uint64_t Value, raw_ostream &OS) const {
|
|
for (unsigned i = 0; i < 8; i++) {
|
|
EmitByte((Value >> (8 * i)) & 0xff, OS);
|
|
}
|
|
}
|
|
|
|
unsigned R600MCCodeEmitter::getHWRegChan(unsigned reg) const {
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|
return MRI.getEncodingValue(reg) >> HW_CHAN_SHIFT;
|
|
}
|
|
|
|
unsigned R600MCCodeEmitter::getHWReg(unsigned RegNo) const {
|
|
return MRI.getEncodingValue(RegNo) & HW_REG_MASK;
|
|
}
|
|
|
|
uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
|
|
const MCOperand &MO,
|
|
SmallVectorImpl<MCFixup> &Fixup) const {
|
|
if (MO.isReg()) {
|
|
if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) {
|
|
return MRI.getEncodingValue(MO.getReg());
|
|
} else {
|
|
return getHWReg(MO.getReg());
|
|
}
|
|
} else if (MO.isImm()) {
|
|
return MO.getImm();
|
|
} else {
|
|
assert(0);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Encoding helper functions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
bool R600MCCodeEmitter::isFCOp(unsigned opcode) const {
|
|
switch(opcode) {
|
|
default: return false;
|
|
case AMDGPU::PREDICATED_BREAK:
|
|
case AMDGPU::CONTINUE:
|
|
case AMDGPU::IF_PREDICATE_SET:
|
|
case AMDGPU::ELSE:
|
|
case AMDGPU::ENDIF:
|
|
case AMDGPU::ENDLOOP:
|
|
case AMDGPU::WHILELOOP:
|
|
return true;
|
|
}
|
|
}
|
|
|
|
bool R600MCCodeEmitter::isTexOp(unsigned opcode) const {
|
|
switch(opcode) {
|
|
default: return false;
|
|
case AMDGPU::TEX_LD:
|
|
case AMDGPU::TEX_GET_TEXTURE_RESINFO:
|
|
case AMDGPU::TEX_SAMPLE:
|
|
case AMDGPU::TEX_SAMPLE_C:
|
|
case AMDGPU::TEX_SAMPLE_L:
|
|
case AMDGPU::TEX_SAMPLE_C_L:
|
|
case AMDGPU::TEX_SAMPLE_LB:
|
|
case AMDGPU::TEX_SAMPLE_C_LB:
|
|
case AMDGPU::TEX_SAMPLE_G:
|
|
case AMDGPU::TEX_SAMPLE_C_G:
|
|
case AMDGPU::TEX_GET_GRADIENTS_H:
|
|
case AMDGPU::TEX_GET_GRADIENTS_V:
|
|
case AMDGPU::TEX_SET_GRADIENTS_H:
|
|
case AMDGPU::TEX_SET_GRADIENTS_V:
|
|
return true;
|
|
}
|
|
}
|
|
|
|
bool R600MCCodeEmitter::isFlagSet(const MCInst &MI, unsigned Operand,
|
|
unsigned Flag) const {
|
|
const MCInstrDesc &MCDesc = MCII.get(MI.getOpcode());
|
|
unsigned FlagIndex = GET_FLAG_OPERAND_IDX(MCDesc.TSFlags);
|
|
if (FlagIndex == 0) {
|
|
return false;
|
|
}
|
|
assert(MI.getOperand(FlagIndex).isImm());
|
|
return !!((MI.getOperand(FlagIndex).getImm() >>
|
|
(NUM_MO_FLAGS * Operand)) & Flag);
|
|
}
|
|
|
|
#include "AMDGPUGenMCCodeEmitter.inc"
|