Ahmed Bougacha 3c9fb6e1ad [AArch64] Improve codegen of store lane instructions by avoiding GPR usage. ... We used to generate code similar to: umov.b w8, v0[2] strb w8, [x0, x1] because the STR*ro* patterns were preferred to ST1*. Instead, we can avoid going through GPRs, and generate: add x8, x0, x1 st1.b { v0 }[2], [x8] This patch increases the ST1* AddedComplexity to achieve that. rdar://16372710 Differential Revision: http://reviews.llvm.org/D6202 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225183 91177308-0d34-0410-b5e6-96231b3b80d8		2015-01-05 17:10:26 +00:00
..
Analysis	[PM] Don't run the machinery of invalidating all the analysis passes	2015-01-05 12:32:11 +00:00
AsmParser
Bitcode	[PM] Switch the new pass manager to use a reference-based API for IR	2015-01-05 02:47:05 +00:00
CodeGen	Replace several 'assert(false' with 'llvm_unreachable' or fold a condition into the assert.	2015-01-05 10:15:49 +00:00
DebugInfo
ExecutionEngine	RTDyldMemoryManager.cpp: Make the reference to __morestack weak.	2014-12-30 22:52:33 +00:00
IR	[PM] Don't run the machinery of invalidating all the analysis passes	2015-01-05 12:32:11 +00:00
IRReader
LineEditor
Linker
LTO
MC	Add r224985 back with a fix.	2014-12-31 17:19:34 +00:00
Object	Add printing the LC_THREAD load commands with llvm-objdump’s -private-headers.	2014-12-23 22:56:39 +00:00
Option
ProfileData
Support	[APFloat][ADT] Fix sign handling logic for FMA results that truncate to zero.	2015-01-04 01:20:55 +00:00
TableGen
Target	[AArch64] Improve codegen of store lane instructions by avoiding GPR usage.	2015-01-05 17:10:26 +00:00
Transforms	Replace several 'assert(false' with 'llvm_unreachable' or fold a condition into the assert.	2015-01-05 10:15:49 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile