Ahmed Bougacha 3c9fb6e1ad [AArch64] Improve codegen of store lane instructions by avoiding GPR usage. ... We used to generate code similar to: umov.b w8, v0[2] strb w8, [x0, x1] because the STR*ro* patterns were preferred to ST1*. Instead, we can avoid going through GPRs, and generate: add x8, x0, x1 st1.b { v0 }[2], [x8] This patch increases the ST1* AddedComplexity to achieve that. rdar://16372710 Differential Revision: http://reviews.llvm.org/D6202 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225183 91177308-0d34-0410-b5e6-96231b3b80d8		2015-01-05 17:10:26 +00:00
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AArch64	[AArch64] Improve codegen of store lane instructions by avoiding GPR usage.	2015-01-05 17:10:26 +00:00
ARM	Emit the build attribute Tag_conformance.	2015-01-05 13:12:17 +00:00
CPP
Generic
Hexagon	[Hexagon] Adding reg-reg indexed load forms.	2014-12-30 18:58:47 +00:00
Inputs
Mips
MSP430
NVPTX
PowerPC	[PowerPC] Enable speculation of cttz/ctlz	2015-01-05 05:24:42 +00:00
R600
SPARC
SystemZ
Thumb
Thumb2
X86	[X86][SSE] Added vector packing test for pr12412	2015-01-04 19:08:03 +00:00
XCore