llvm-6502

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Daniel Sanders 3cb4a1cbcb Merging r230956:

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r230956 | vkalintiris | 2015-03-02 12:47:32 +0000 (Mon, 02 Mar 2015) | 10 lines

[mips] Optimize conditional moves where RHS is zero.

Summary:
When the RHS of a conditional move node is zero, we can utilize the $zero
register by inverting the conditional move instruction and by swapping the
order of its True/False operands.

Reviewers: dsanders

Differential Revision: http://reviews.llvm.org/D7945
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235886 91177308-0d34-0410-b5e6-96231b3b80d8

2015-04-27 14:57:52 +00:00

AArch64

Cherry-pick r231227: fix PR22408.

2015-04-08 07:19:32 +00:00

ARM

Merging r228518:

2015-02-09 02:38:04 +00:00

CPP

…

Generic

CodeGen: do not attempt to invalidate virtual registers for zero-sized phis.

2014-12-19 20:50:07 +00:00