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https://github.com/c64scene-ar/llvm-6502.git
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f35ce2376c
The old method used by X86TTI to determine partial-unrolling thresholds was messy (because it worked by testing target features), and also would not correctly identify the target CPU if certain target features were disabled. After some discussions on IRC with Chandler et al., it was decided that the processor scheduling models were the right containers for this information (because it is often tied to special uop dispatch-buffer sizes). This does represent a small functionality change: - For generic x86-64 (which uses the SB model and, thus, will get some unrolling). - For AMD cores (because they still currently use the SB scheduling model) - For Haswell (based on benchmarking by Louis Gerbarg, it was decided to bump the default threshold to 50; we're working on a test case for this). Otherwise, nothing has changed for any other targets. The logic, however, has been moved into BasicTTI, so other targets may now also opt-in to this functionality simply by setting LoopMicroOpBufferSize in their processor model definitions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208289 91177308-0d34-0410-b5e6-96231b3b80d8
128 lines
4.7 KiB
LLVM
128 lines
4.7 KiB
LLVM
; RUN: opt < %s -S -loop-unroll -mcpu=nehalem | FileCheck %s
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; RUN: opt < %s -S -loop-unroll -mcpu=core -unroll-runtime=0 | FileCheck -check-prefix=CHECK-NOUNRL %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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define void @foo(i32* noalias nocapture readnone %ip, double %alpha, double* noalias nocapture %a, double* noalias nocapture readonly %b) #0 {
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entry:
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br label %vector.body
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vector.body: ; preds = %vector.body, %entry
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%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
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%0 = getelementptr inbounds double* %b, i64 %index
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%1 = bitcast double* %0 to <2 x double>*
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%wide.load = load <2 x double>* %1, align 8
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%.sum9 = or i64 %index, 2
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%2 = getelementptr double* %b, i64 %.sum9
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%3 = bitcast double* %2 to <2 x double>*
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%wide.load8 = load <2 x double>* %3, align 8
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%4 = fadd <2 x double> %wide.load, <double 1.000000e+00, double 1.000000e+00>
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%5 = fadd <2 x double> %wide.load8, <double 1.000000e+00, double 1.000000e+00>
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%6 = getelementptr inbounds double* %a, i64 %index
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%7 = bitcast double* %6 to <2 x double>*
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store <2 x double> %4, <2 x double>* %7, align 8
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%.sum10 = or i64 %index, 2
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%8 = getelementptr double* %a, i64 %.sum10
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%9 = bitcast double* %8 to <2 x double>*
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store <2 x double> %5, <2 x double>* %9, align 8
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%index.next = add i64 %index, 4
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%10 = icmp eq i64 %index.next, 1600
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br i1 %10, label %for.end, label %vector.body
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; FIXME: We should probably unroll this loop by a factor of 2, but the cost
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; model needs to be fixed to account for instructions likely to be folded
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; as part of an addressing mode.
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; CHECK-LABEL: @foo
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; CHECK-NOUNRL-LABEL: @foo
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for.end: ; preds = %vector.body
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ret void
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}
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define void @bar(i32* noalias nocapture readnone %ip, double %alpha, double* noalias nocapture %a, double* noalias nocapture readonly %b) #0 {
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entry:
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br label %vector.body
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vector.body: ; preds = %vector.body, %entry
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%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
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%v0 = getelementptr inbounds double* %b, i64 %index
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%v1 = bitcast double* %v0 to <2 x double>*
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%wide.load = load <2 x double>* %v1, align 8
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%v4 = fadd <2 x double> %wide.load, <double 1.000000e+00, double 1.000000e+00>
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%v5 = fmul <2 x double> %v4, <double 8.000000e+00, double 8.000000e+00>
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%v6 = getelementptr inbounds double* %a, i64 %index
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%v7 = bitcast double* %v6 to <2 x double>*
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store <2 x double> %v5, <2 x double>* %v7, align 8
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%index.next = add i64 %index, 2
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%v10 = icmp eq i64 %index.next, 1600
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br i1 %v10, label %for.end, label %vector.body
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; FIXME: We should probably unroll this loop by a factor of 2, but the cost
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; model needs to first to fixed to account for instructions likely to be folded
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; as part of an addressing mode.
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; CHECK-LABEL: @bar
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; CHECK: fadd
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; CHECK-NEXT: fmul
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; CHECK: fadd
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; CHECK-NEXT: fmul
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; CHECK-NOUNRL-LABEL: @bar
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; CHECK-NOUNRL: fadd
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; CHECK-NOUNRL-NEXT: fmul
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; CHECK-NOUNRL-NOT: fadd
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for.end: ; preds = %vector.body
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ret void
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}
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define zeroext i16 @test1(i16* nocapture readonly %arr, i32 %n) #0 {
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entry:
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%cmp25 = icmp eq i32 %n, 0
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br i1 %cmp25, label %for.end, label %for.body
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for.body: ; preds = %entry, %for.body
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
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%reduction.026 = phi i16 [ %add14, %for.body ], [ 0, %entry ]
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%arrayidx = getelementptr inbounds i16* %arr, i64 %indvars.iv
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%0 = load i16* %arrayidx, align 2
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%add = add i16 %0, %reduction.026
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%sext = mul i64 %indvars.iv, 12884901888
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%idxprom3 = ashr exact i64 %sext, 32
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%arrayidx4 = getelementptr inbounds i16* %arr, i64 %idxprom3
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%1 = load i16* %arrayidx4, align 2
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%add7 = add i16 %add, %1
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%sext28 = mul i64 %indvars.iv, 21474836480
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%idxprom10 = ashr exact i64 %sext28, 32
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%arrayidx11 = getelementptr inbounds i16* %arr, i64 %idxprom10
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%2 = load i16* %arrayidx11, align 2
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%add14 = add i16 %add7, %2
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp eq i32 %lftr.wideiv, %n
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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%reduction.0.lcssa = phi i16 [ 0, %entry ], [ %add14, %for.body ]
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ret i16 %reduction.0.lcssa
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; This loop is too large to be partially unrolled (size=16)
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; CHECK-LABEL: @test1
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; CHECK: br
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; CHECK: br
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; CHECK: br
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; CHECK: br
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; CHECK-NOT: br
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; CHECK-NOUNRL-LABEL: @test1
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; CHECK-NOUNRL: br
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; CHECK-NOUNRL: br
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; CHECK-NOUNRL: br
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; CHECK-NOUNRL: br
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; CHECK-NOUNRL-NOT: br
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}
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attributes #0 = { nounwind uwtable }
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