llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-21 21:29:41 +00:00

History

Chandler Carruth 4bbf21e71e [x86] Improve and correct how the new vector shuffle lowering was

matching and lowering 64-bit insertions.

The first problem was that we weren't looking through bitcasts to
discover that we *could* lower as insertions. Once fixed, we in turn
weren't looking through bitcasts to discover that we could fold a load
into the lowering. Once fixed, we weren't forming a SCALAR_TO_VECTOR
node around the inserted element and instead were passing a scalar to
a DAG node that expected a vector. It turns out there are some patterns
that will "lower" this into the correct asm, but the rest of the X86
backend is very unhappy with such antics.

This should fix a few more edge case regressions I've spotted going
through the regression test suite to enable the new vector shuffle
lowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218839 91177308-0d34-0410-b5e6-96231b3b80d8

2014-10-01 23:14:28 +00:00

Analysis

Move the complex address expression out of DIVariable and into an extra

2014-10-01 18:55:02 +00:00

Assembler

Move the complex address expression out of DIVariable and into an extra

2014-10-01 18:55:02 +00:00

Bindings

Extend C disassembler API to allow specifying target features

2014-09-30 16:31:40 +00:00

Bitcode

Ensure bitcode encoding stays stable.