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f98f2ce29e
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
64 lines
1.9 KiB
C++
64 lines
1.9 KiB
C++
//===-- AMDGPURegisterInfo.h - AMDGPURegisterInfo Interface -*- C++ -*-----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief TargetRegisterInfo interface that is implemented by all hw codegen
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/// targets.
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//
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//===----------------------------------------------------------------------===//
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#ifndef AMDGPUREGISTERINFO_H
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#define AMDGPUREGISTERINFO_H
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#include "llvm/ADT/BitVector.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#define GET_REGINFO_HEADER
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#define GET_REGINFO_ENUM
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#include "AMDGPUGenRegisterInfo.inc"
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namespace llvm {
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class AMDGPUTargetMachine;
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class TargetInstrInfo;
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struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
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TargetMachine &TM;
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const TargetInstrInfo &TII;
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static const uint16_t CalleeSavedReg;
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AMDGPURegisterInfo(TargetMachine &tm, const TargetInstrInfo &tii);
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virtual BitVector getReservedRegs(const MachineFunction &MF) const {
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assert(!"Unimplemented"); return BitVector();
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}
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/// \param RC is an AMDIL reg class.
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///
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/// \returns The ISA reg class that is equivalent to \p RC.
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virtual const TargetRegisterClass * getISARegClass(
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const TargetRegisterClass * RC) const {
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assert(!"Unimplemented"); return NULL;
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}
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virtual const TargetRegisterClass* getCFGStructurizerRegClass(MVT VT) const {
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assert(!"Unimplemented"); return NULL;
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}
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const uint16_t* getCalleeSavedRegs(const MachineFunction *MF) const;
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void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
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RegScavenger *RS) const;
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unsigned getFrameRegister(const MachineFunction &MF) const;
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};
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} // End namespace llvm
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#endif // AMDIDSAREGISTERINFO_H
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