mirror of
https://github.com/c64scene-ar/llvm-6502.git
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29f94c7201
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
146 lines
6.8 KiB
LLVM
146 lines
6.8 KiB
LLVM
; RUN: llc -march=arm64 -aarch64-neon-syntax=apple -o - %s| FileCheck %s
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define <16 x i8> @foov16i8(<8 x i16> %a0, <8 x i16> %b0) nounwind readnone ssp {
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; CHECK-LABEL: foov16i8:
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%vshrn_low_shift = lshr <8 x i16> %a0, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
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%vshrn_low = trunc <8 x i16> %vshrn_low_shift to <8 x i8>
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%vshrn_high_shift = lshr <8 x i16> %b0, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
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%vshrn_high = trunc <8 x i16> %vshrn_high_shift to <8 x i8>
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; CHECK: shrn.8b v0, v0, #5
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; CHECK-NEXT: shrn2.16b v0, v1, #5
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; CHECK-NEXT: ret
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%1 = bitcast <8 x i8> %vshrn_low to <1 x i64>
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%2 = bitcast <8 x i8> %vshrn_high to <1 x i64>
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%shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>
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%3 = bitcast <2 x i64> %shuffle.i to <16 x i8>
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ret <16 x i8> %3
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}
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define <8 x i16> @foov8i16(<4 x i32> %a0, <4 x i32> %b0) nounwind readnone ssp {
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; CHECK-LABEL: foov8i16:
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%vshrn_low_shift = lshr <4 x i32> %a0, <i32 5, i32 5, i32 5, i32 5>
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%vshrn_low = trunc <4 x i32> %vshrn_low_shift to <4 x i16>
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%vshrn_high_shift = lshr <4 x i32> %b0, <i32 5, i32 5, i32 5, i32 5>
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%vshrn_high = trunc <4 x i32> %vshrn_high_shift to <4 x i16>
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; CHECK: shrn.4h v0, v0, #5
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; CHECK-NEXT: shrn2.8h v0, v1, #5
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; CHECK-NEXT: ret
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%1 = bitcast <4 x i16> %vshrn_low to <1 x i64>
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%2 = bitcast <4 x i16> %vshrn_high to <1 x i64>
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%shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>
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%3 = bitcast <2 x i64> %shuffle.i to <8 x i16>
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ret <8 x i16> %3
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}
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define <4 x i32> @foov4i32(<2 x i64> %a0, <2 x i64> %b0) nounwind readnone ssp {
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; CHECK-LABEL: foov4i32:
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%vshrn_low_shift = lshr <2 x i64> %a0, <i64 5, i64 5>
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%vshrn_low = trunc <2 x i64> %vshrn_low_shift to <2 x i32>
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%vshrn_high_shift = lshr <2 x i64> %b0, <i64 5, i64 5>
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%vshrn_high = trunc <2 x i64> %vshrn_high_shift to <2 x i32>
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; CHECK: shrn.2s v0, v0, #5
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; CHECK-NEXT: shrn2.4s v0, v1, #5
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; CHECK-NEXT: ret
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%1 = bitcast <2 x i32> %vshrn_low to <1 x i64>
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%2 = bitcast <2 x i32> %vshrn_high to <1 x i64>
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%shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>
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%3 = bitcast <2 x i64> %shuffle.i to <4 x i32>
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ret <4 x i32> %3
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}
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define <8 x i16> @bar(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %b0, <4 x i32> %b1) nounwind readnone ssp {
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; CHECK-LABEL: bar:
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%vaddhn2.i = tail call <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32> %a0, <4 x i32> %a1) nounwind
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%vaddhn2.i10 = tail call <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32> %b0, <4 x i32> %b1) nounwind
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; CHECK: addhn.4h v0, v0, v1
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; CHECK-NEXT: addhn2.8h v0, v2, v3
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; CHECK-NEXT: ret
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%1 = bitcast <4 x i16> %vaddhn2.i to <1 x i64>
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%2 = bitcast <4 x i16> %vaddhn2.i10 to <1 x i64>
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%shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>
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%3 = bitcast <2 x i64> %shuffle.i to <8 x i16>
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ret <8 x i16> %3
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}
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define <8 x i16> @baz(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %b0, <4 x i32> %b1) nounwind readnone ssp {
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; CHECK-LABEL: baz:
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%vaddhn2.i = tail call <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32> %a0, <4 x i32> %a1) nounwind
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%vshrn_high_shift = ashr <4 x i32> %b0, <i32 5, i32 5, i32 5, i32 5>
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%vshrn_high = trunc <4 x i32> %vshrn_high_shift to <4 x i16>
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; CHECK: addhn.4h v0, v0, v1
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; CHECK-NEXT: shrn2.8h v0, v2, #5
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; CHECK-NEXT: ret
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%1 = bitcast <4 x i16> %vaddhn2.i to <1 x i64>
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%2 = bitcast <4 x i16> %vshrn_high to <1 x i64>
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%shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>
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%3 = bitcast <2 x i64> %shuffle.i to <8 x i16>
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ret <8 x i16> %3
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}
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define <8 x i16> @raddhn(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %b0, <4 x i32> %b1) nounwind readnone ssp {
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; CHECK-LABEL: raddhn:
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entry:
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; CHECK: raddhn.4h v0, v0, v1
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; CHECK-NEXT: raddhn2.8h v0, v2, v3
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; CHECK-NEXT: ret
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%vraddhn2.i = tail call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %a0, <4 x i32> %a1) nounwind
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%vraddhn2.i10 = tail call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %b0, <4 x i32> %b1) nounwind
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%0 = bitcast <4 x i16> %vraddhn2.i to <1 x i64>
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%1 = bitcast <4 x i16> %vraddhn2.i10 to <1 x i64>
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%shuffle.i = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>
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%2 = bitcast <2 x i64> %shuffle.i to <8 x i16>
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ret <8 x i16> %2
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}
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define <8 x i16> @vrshrn(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> %b0, <8 x i16> %b1) nounwind readnone ssp {
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; CHECK-LABEL: vrshrn:
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; CHECK: rshrn.8b v0, v0, #5
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; CHECK-NEXT: rshrn2.16b v0, v2, #6
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; CHECK-NEXT: ret
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%vrshrn_n1 = tail call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %a0, i32 5)
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%vrshrn_n4 = tail call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %b0, i32 6)
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%1 = bitcast <8 x i8> %vrshrn_n1 to <1 x i64>
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%2 = bitcast <8 x i8> %vrshrn_n4 to <1 x i64>
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%shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>
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%3 = bitcast <2 x i64> %shuffle.i to <8 x i16>
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ret <8 x i16> %3
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}
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define <8 x i16> @vrsubhn(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> %b0, <8 x i16> %b1) nounwind readnone ssp {
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; CHECK-LABEL: vrsubhn:
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; CHECK: rsubhn.8b v0, v0, v1
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; CHECK: rsubhn2.16b v0, v2, v3
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; CHECK-NEXT: ret
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%vrsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a0, <8 x i16> %a1) nounwind
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%vrsubhn2.i10 = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %b0, <8 x i16> %b1) nounwind
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%1 = bitcast <8 x i8> %vrsubhn2.i to <1 x i64>
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%2 = bitcast <8 x i8> %vrsubhn2.i10 to <1 x i64>
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%shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>
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%3 = bitcast <2 x i64> %shuffle.i to <8 x i16>
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ret <8 x i16> %3
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}
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define <8 x i16> @noOpt1(<2 x i32> %a0, <2 x i32> %a1, <4 x i32> %b0, <4 x i32> %b1) nounwind readnone ssp {
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; CHECK-LABEL: noOpt1:
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%vqsub2.i = tail call <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32> %a0, <2 x i32> %a1) nounwind
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%vaddhn2.i = tail call <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32> %b0, <4 x i32> %b1) nounwind
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; CHECK: sqsub.2s v0, v0, v1
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; CHECK-NEXT: addhn2.8h v0, v2, v3
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%1 = bitcast <2 x i32> %vqsub2.i to <1 x i64>
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%2 = bitcast <4 x i16> %vaddhn2.i to <1 x i64>
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%shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %2, <2 x i32> <i32 0, i32 1>
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%3 = bitcast <2 x i64> %shuffle.i to <8 x i16>
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ret <8 x i16> %3
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}
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declare <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
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declare <8 x i8> @llvm.aarch64.neon.shrn.v8i8(<8 x i16>, i32) nounwind readnone
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declare <4 x i16> @llvm.aarch64.neon.shrn.v4i16(<4 x i32>, i32) nounwind readnone
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declare <2 x i32> @llvm.aarch64.neon.shrn.v2i32(<2 x i64>, i32) nounwind readnone
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declare <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
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declare <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
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declare <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16>, i32) nounwind readnone
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declare <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
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